6048caab6b
We've always considered the mpcore timers to be a single monolithic device and we defined our own fdt binding for it with our own compat string. The published bindings treat the timers as two separate devices, a global timer and a "timer-watchdog" device for the per-cpu private timers. Thus our binding has two tuples in the regs property, one set of registers for the global timer and one for the private timers. The published bindings have two separate devices, each with a single set of registers. (Note that we don't use the optional watchdog feature of the hardware.) These changes add the compat strings for the published bindings. If our own compat string appears, we expect to get two sets of memory resources. For the published bindings, there's only one set of memory resources, and only the private timers have an associated interrupt. The other major change is that there can no longer be a single global var for the softc pointer because now there may be multiple devices at runtime. Since the global timer is used only as a timecounter and the private timers only as eventtimers, and there will only be one of each, those are now the pointers which are global, and the priv fields of those structures backlink to the device softc. |
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| .. | ||
| allwinner | ||
| altera/socfpga | ||
| arm | ||
| at91 | ||
| broadcom/bcm2835 | ||
| cavium/cns11xx | ||
| conf | ||
| freescale | ||
| include | ||
| lpc | ||
| mv | ||
| rockchip | ||
| s3c2xx0 | ||
| samsung/exynos | ||
| ti | ||
| versatile | ||
| xilinx | ||
| xscale | ||