728 lines
28 KiB
C++
728 lines
28 KiB
C++
//===- utils/TableGen/X86FoldTablesEmitter.cpp - X86 backend-*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting the memory fold tables of
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// the X86 backend instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenDAGPatterns.h"
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#include "CodeGenTarget.h"
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#include "X86RecognizableInstr.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/TableGenBackend.h"
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using namespace llvm;
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namespace {
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// 3 possible strategies for the unfolding flag (TB_NO_REVERSE) of the
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// manual added entries.
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enum UnfoldStrategy {
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UNFOLD, // Allow unfolding
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NO_UNFOLD, // Prevent unfolding
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NO_STRATEGY // Make decision according to operands' sizes
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};
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// Represents an entry in the manual mapped instructions set.
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struct ManualMapEntry {
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const char *RegInstStr;
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const char *MemInstStr;
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UnfoldStrategy Strategy;
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ManualMapEntry(const char *RegInstStr, const char *MemInstStr,
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UnfoldStrategy Strategy = NO_STRATEGY)
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: RegInstStr(RegInstStr), MemInstStr(MemInstStr), Strategy(Strategy) {}
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};
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class IsMatch;
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// List of instructions requiring explicitly aligned memory.
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const char *const ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS",
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"MOVNTPD", "MOVNTDQ", "MOVNTDQA"};
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// List of instructions NOT requiring explicit memory alignment.
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const char *const ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD"};
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// For manually mapping instructions that do not match by their encoding.
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const ManualMapEntry ManualMapSet[] = {
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{ "ADD16ri_DB", "ADD16mi", NO_UNFOLD },
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{ "ADD16ri8_DB", "ADD16mi8", NO_UNFOLD },
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{ "ADD16rr_DB", "ADD16mr", NO_UNFOLD },
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{ "ADD32ri_DB", "ADD32mi", NO_UNFOLD },
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{ "ADD32ri8_DB", "ADD32mi8", NO_UNFOLD },
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{ "ADD32rr_DB", "ADD32mr", NO_UNFOLD },
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{ "ADD64ri32_DB", "ADD64mi32", NO_UNFOLD },
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{ "ADD64ri8_DB", "ADD64mi8", NO_UNFOLD },
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{ "ADD64rr_DB", "ADD64mr", NO_UNFOLD },
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{ "ADD16rr_DB", "ADD16rm", NO_UNFOLD },
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{ "ADD32rr_DB", "ADD32rm", NO_UNFOLD },
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{ "ADD64rr_DB", "ADD64rm", NO_UNFOLD },
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{ "PUSH16r", "PUSH16rmm", NO_UNFOLD },
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{ "PUSH32r", "PUSH32rmm", NO_UNFOLD },
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{ "PUSH64r", "PUSH64rmm", NO_UNFOLD },
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{ "TAILJMPr", "TAILJMPm", UNFOLD },
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{ "TAILJMPr64", "TAILJMPm64", UNFOLD },
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{ "TAILJMPr64_REX", "TAILJMPm64_REX", UNFOLD },
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};
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// Do not add these instructions to any of the folding tables.
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const char *const NoFoldSet[] = {
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"TCRETURNri64",
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"TCRETURNmi64", // Special dealing (in X86InstrCompiler.td under
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"TCRETURNri", // "tailcall stuff" section).
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"TCRETURNmi",
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// Never fold XCHG, the register and memory forms have different locking
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// semantics.
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"XCHG8rr", "XCHG8rm",
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"XCHG16rr", "XCHG16rm",
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"XCHG32rr", "XCHG32rm",
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"XCHG64rr", "XCHG64rm",
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// Different calculations of the folded operand between
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// memory and register forms (folding is illegal).
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// - In their register form, the second register operand's relevant
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// bits are only the first 4/5/6 (depending on mode and reg size).
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// - In their memory form, the second register operand's relevant
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// bits are only the first 16/32/64 (depending on mode and reg size).
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"BT16rr", "BT32rr", "BT64rr",
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"BT16mr", "BT32mr", "BT64mr",
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"BTC16rr", "BTC32rr", "BTC64rr",
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"BTC16mr", "BTC32mr", "BTC64mr",
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"BTR16rr", "BTR32rr", "BTR64rr",
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"BTR16mr", "BTR32mr", "BTR64mr",
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"BTS16rr", "BTS32rr", "BTS64rr",
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"BTS16mr", "BTS32mr", "BTS64mr",
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// Memory folding is enabled only when optimizing for size by DAG
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// patterns only. (issue detailed in D28744 review)
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"VCVTSS2SDrm", "VCVTSS2SDrr",
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"VCVTSS2SDZrm", "VCVTSS2SDZrr",
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"VCVTSS2SDZrmk", "VCVTSS2SDZrrk",
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"VCVTSS2SDZrmkz", "VCVTSS2SDZrrkz",
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"VCVTSS2SDZrm_Int", "VCVTSS2SDZrr_Int",
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"VCVTSS2SDZrm_Intk", "VCVTSS2SDZrr_Intk",
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"VCVTSS2SDZrm_Intkz", "VCVTSS2SDZrr_Intkz",
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"VCVTSD2SSrm", "VCVTSD2SSrr",
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"VCVTSD2SSZrm", "VCVTSD2SSZrr",
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"VCVTSD2SSZrmk", "VCVTSD2SSZrrk",
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"VCVTSD2SSZrmkz", "VCVTSD2SSZrrkz",
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"VCVTSD2SSZrm_Int", "VCVTSD2SSZrr_Int",
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"VCVTSD2SSZrm_Intk", "VCVTSD2SSZrr_Intk",
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"VCVTSD2SSZrm_Intkz", "VCVTSD2SSZrr_Intkz",
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"VRCP14SSrm", "VRCP14SSrr",
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"VRCP14SDrm", "VRCP14SDrr",
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"VRSQRT14SSrm", "VRSQRT14SSrr",
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"VRSQRT14SDrm", "VRSQRT14SDrr",
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"VSQRTSSm", "VSQRTSSr",
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"VSQRTSSm_Int", "VSQRTSSr_Int",
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"VSQRTSSZm", "VSQRTSSZr",
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"VSQRTSSZm_Int", "VSQRTSSZr_Int",
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"VSQRTSSZm_Intk", "VSQRTSSZr_Intk",
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"VSQRTSSZm_Intkz", "VSQRTSSZr_Intkz",
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"VSQRTSDm", "VSQRTSDr",
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"VSQRTSDm_Int", "VSQRTSDr_Int",
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"VSQRTSDZm", "VSQRTSDZr",
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"VSQRTSDZm_Int", "VSQRTSDZr_Int",
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"VSQRTSDZm_Intk", "VSQRTSDZr_Intk",
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"VSQRTSDZm_Intkz", "VSQRTSDZr_Intkz",
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};
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static bool isExplicitAlign(const CodeGenInstruction *Inst) {
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return any_of(ExplicitAlign, [Inst](const char *InstStr) {
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return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
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});
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}
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static bool isExplicitUnalign(const CodeGenInstruction *Inst) {
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return any_of(ExplicitUnalign, [Inst](const char *InstStr) {
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return Inst->TheDef->getName().find(InstStr) != StringRef::npos;
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});
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}
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class X86FoldTablesEmitter {
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RecordKeeper &Records;
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CodeGenTarget Target;
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// Represents an entry in the folding table
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class X86FoldTableEntry {
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const CodeGenInstruction *RegInst;
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const CodeGenInstruction *MemInst;
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public:
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bool CannotUnfold = false;
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bool IsLoad = false;
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bool IsStore = false;
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bool IsAligned = false;
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unsigned int Alignment = 0;
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X86FoldTableEntry(const CodeGenInstruction *RegInst,
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const CodeGenInstruction *MemInst)
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: RegInst(RegInst), MemInst(MemInst) {}
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friend raw_ostream &operator<<(raw_ostream &OS,
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const X86FoldTableEntry &E) {
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OS << "{ X86::" << E.RegInst->TheDef->getName()
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<< ", X86::" << E.MemInst->TheDef->getName() << ", ";
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if (E.IsLoad)
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OS << "TB_FOLDED_LOAD | ";
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if (E.IsStore)
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OS << "TB_FOLDED_STORE | ";
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if (E.CannotUnfold)
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OS << "TB_NO_REVERSE | ";
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if (E.IsAligned)
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OS << "TB_ALIGN_" << E.Alignment << " | ";
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OS << "0 },\n";
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return OS;
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}
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};
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typedef std::vector<X86FoldTableEntry> FoldTable;
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// std::vector for each folding table.
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// Table2Addr - Holds instructions which their memory form performs load+store
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// Table#i - Holds instructions which the their memory form perform a load OR
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// a store, and their #i'th operand is folded.
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FoldTable Table2Addr;
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FoldTable Table0;
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FoldTable Table1;
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FoldTable Table2;
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FoldTable Table3;
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FoldTable Table4;
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public:
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X86FoldTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
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// run - Generate the 6 X86 memory fold tables.
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void run(raw_ostream &OS);
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private:
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// Decides to which table to add the entry with the given instructions.
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// S sets the strategy of adding the TB_NO_REVERSE flag.
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void updateTables(const CodeGenInstruction *RegInstr,
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const CodeGenInstruction *MemInstr,
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const UnfoldStrategy S = NO_STRATEGY);
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// Generates X86FoldTableEntry with the given instructions and fill it with
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// the appropriate flags - then adds it to Table.
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void addEntryWithFlags(FoldTable &Table, const CodeGenInstruction *RegInstr,
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const CodeGenInstruction *MemInstr,
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const UnfoldStrategy S, const unsigned int FoldedInd);
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// Print the given table as a static const C++ array of type
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// X86MemoryFoldTableEntry.
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void printTable(const FoldTable &Table, std::string TableName,
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raw_ostream &OS) {
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OS << "\nstatic const X86MemoryFoldTableEntry MemoryFold" << TableName
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<< "[] = {\n";
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for (const X86FoldTableEntry &E : Table)
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OS.indent(2) << E;
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OS << "};\n";
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}
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};
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// Return true if one of the instruction's operands is a RST register class
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static bool hasRSTRegClass(const CodeGenInstruction *Inst) {
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return any_of(Inst->Operands, [](const CGIOperandList::OperandInfo &OpIn) {
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return OpIn.Rec->getName() == "RST";
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});
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}
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// Return true if one of the instruction's operands is a ptr_rc_tailcall
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static bool hasPtrTailcallRegClass(const CodeGenInstruction *Inst) {
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return any_of(Inst->Operands, [](const CGIOperandList::OperandInfo &OpIn) {
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return OpIn.Rec->getName() == "ptr_rc_tailcall";
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});
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}
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// Calculates the integer value representing the BitsInit object
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static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
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assert(B->getNumBits() <= sizeof(uint64_t) * CHAR_BIT &&
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"BitInits' too long!");
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uint64_t Value = 0;
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for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
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BitInit *Bit = cast<BitInit>(B->getBit(i));
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Value |= uint64_t(Bit->getValue()) << i;
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}
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return Value;
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}
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// Returns true if the two given BitsInits represent the same integer value
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static inline bool equalBitsInits(const BitsInit *B1, const BitsInit *B2) {
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if (B1->getNumBits() != B2->getNumBits())
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PrintFatalError("Comparing two BitsInits with different sizes!");
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for (unsigned i = 0, e = B1->getNumBits(); i != e; ++i) {
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BitInit *Bit1 = cast<BitInit>(B1->getBit(i));
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BitInit *Bit2 = cast<BitInit>(B2->getBit(i));
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if (Bit1->getValue() != Bit2->getValue())
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return false;
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}
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return true;
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}
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// Return the size of the register operand
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static inline unsigned int getRegOperandSize(const Record *RegRec) {
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if (RegRec->isSubClassOf("RegisterOperand"))
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RegRec = RegRec->getValueAsDef("RegClass");
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if (RegRec->isSubClassOf("RegisterClass"))
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return RegRec->getValueAsListOfDefs("RegTypes")[0]->getValueAsInt("Size");
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llvm_unreachable("Register operand's size not known!");
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}
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// Return the size of the memory operand
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static inline unsigned int
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getMemOperandSize(const Record *MemRec, const bool IntrinsicSensitive = false) {
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if (MemRec->isSubClassOf("Operand")) {
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// Intrinsic memory instructions use ssmem/sdmem.
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if (IntrinsicSensitive &&
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(MemRec->getName() == "sdmem" || MemRec->getName() == "ssmem"))
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return 128;
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std::string Name =
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MemRec->getValueAsDef("ParserMatchClass")->getValueAsString("Name");
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if (Name == "Mem8")
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return 8;
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if (Name == "Mem16")
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return 16;
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if (Name == "Mem32")
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return 32;
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if (Name == "Mem64")
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return 64;
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if (Name == "Mem80")
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return 80;
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if (Name == "Mem128")
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return 128;
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if (Name == "Mem256")
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return 256;
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if (Name == "Mem512")
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return 512;
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}
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llvm_unreachable("Memory operand's size not known!");
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}
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// Returns true if the record's list of defs includes the given def.
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static inline bool hasDefInList(const Record *Rec, const StringRef List,
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const StringRef Def) {
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if (!Rec->isValueUnset(List)) {
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return any_of(*(Rec->getValueAsListInit(List)),
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[Def](const Init *I) { return I->getAsString() == Def; });
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}
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return false;
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}
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// Return true if the instruction defined as a register flavor.
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static inline bool hasRegisterFormat(const Record *Inst) {
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const BitsInit *FormBits = Inst->getValueAsBitsInit("FormBits");
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uint64_t FormBitsNum = getValueFromBitsInit(FormBits);
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// Values from X86Local namespace defined in X86RecognizableInstr.cpp
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return FormBitsNum >= X86Local::MRMDestReg && FormBitsNum <= X86Local::MRM7r;
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}
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// Return true if the instruction defined as a memory flavor.
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static inline bool hasMemoryFormat(const Record *Inst) {
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const BitsInit *FormBits = Inst->getValueAsBitsInit("FormBits");
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uint64_t FormBitsNum = getValueFromBitsInit(FormBits);
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// Values from X86Local namespace defined in X86RecognizableInstr.cpp
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return FormBitsNum >= X86Local::MRMDestMem && FormBitsNum <= X86Local::MRM7m;
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}
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static inline bool isNOREXRegClass(const Record *Op) {
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return Op->getName().find("_NOREX") != StringRef::npos;
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}
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static inline bool isRegisterOperand(const Record *Rec) {
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return Rec->isSubClassOf("RegisterClass") ||
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Rec->isSubClassOf("RegisterOperand") ||
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Rec->isSubClassOf("PointerLikeRegClass");
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}
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static inline bool isMemoryOperand(const Record *Rec) {
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return Rec->isSubClassOf("Operand") &&
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Rec->getValueAsString("OperandType") == "OPERAND_MEMORY";
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}
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static inline bool isImmediateOperand(const Record *Rec) {
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return Rec->isSubClassOf("Operand") &&
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Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE";
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}
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// Get the alternative instruction pointed by "FoldGenRegForm" field.
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static inline const CodeGenInstruction *
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getAltRegInst(const CodeGenInstruction *I, const RecordKeeper &Records,
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const CodeGenTarget &Target) {
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std::string AltRegInstStr = I->TheDef->getValueAsString("FoldGenRegForm");
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Record *AltRegInstRec = Records.getDef(AltRegInstStr);
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assert(AltRegInstRec &&
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"Alternative register form instruction def not found");
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CodeGenInstruction &AltRegInst = Target.getInstruction(AltRegInstRec);
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return &AltRegInst;
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}
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// Function object - Operator() returns true if the given VEX instruction
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// matches the EVEX instruction of this object.
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class IsMatch {
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const CodeGenInstruction *MemInst;
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const RecordKeeper &Records;
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public:
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IsMatch(const CodeGenInstruction *Inst, const RecordKeeper &Records)
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: MemInst(Inst), Records(Records) {}
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bool operator()(const CodeGenInstruction *RegInst) {
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Record *MemRec = MemInst->TheDef;
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Record *RegRec = RegInst->TheDef;
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// Return false if one (at least) of the encoding fields of both
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// instructions do not match.
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if (RegRec->getValueAsDef("OpEnc") != MemRec->getValueAsDef("OpEnc") ||
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!equalBitsInits(RegRec->getValueAsBitsInit("Opcode"),
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MemRec->getValueAsBitsInit("Opcode")) ||
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// VEX/EVEX fields
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RegRec->getValueAsDef("OpPrefix") !=
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MemRec->getValueAsDef("OpPrefix") ||
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RegRec->getValueAsDef("OpMap") != MemRec->getValueAsDef("OpMap") ||
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RegRec->getValueAsDef("OpSize") != MemRec->getValueAsDef("OpSize") ||
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RegRec->getValueAsBit("hasVEX_4V") !=
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MemRec->getValueAsBit("hasVEX_4V") ||
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RegRec->getValueAsBit("hasEVEX_K") !=
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MemRec->getValueAsBit("hasEVEX_K") ||
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RegRec->getValueAsBit("hasEVEX_Z") !=
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MemRec->getValueAsBit("hasEVEX_Z") ||
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RegRec->getValueAsBit("hasEVEX_B") !=
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MemRec->getValueAsBit("hasEVEX_B") ||
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RegRec->getValueAsBit("hasEVEX_RC") !=
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MemRec->getValueAsBit("hasEVEX_RC") ||
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RegRec->getValueAsBit("hasREX_WPrefix") !=
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MemRec->getValueAsBit("hasREX_WPrefix") ||
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RegRec->getValueAsBit("hasLockPrefix") !=
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MemRec->getValueAsBit("hasLockPrefix") ||
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!equalBitsInits(RegRec->getValueAsBitsInit("EVEX_LL"),
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MemRec->getValueAsBitsInit("EVEX_LL")) ||
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!equalBitsInits(RegRec->getValueAsBitsInit("VEX_WPrefix"),
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MemRec->getValueAsBitsInit("VEX_WPrefix")) ||
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// Instruction's format - The register form's "Form" field should be
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// the opposite of the memory form's "Form" field.
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!areOppositeForms(RegRec->getValueAsBitsInit("FormBits"),
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MemRec->getValueAsBitsInit("FormBits")) ||
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RegRec->getValueAsBit("isAsmParserOnly") !=
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MemRec->getValueAsBit("isAsmParserOnly"))
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return false;
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// Make sure the sizes of the operands of both instructions suit each other.
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// This is needed for instructions with intrinsic version (_Int).
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// Where the only difference is the size of the operands.
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// For example: VUCOMISDZrm and Int_VUCOMISDrm
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// Also for instructions that their EVEX version was upgraded to work with
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// k-registers. For example VPCMPEQBrm (xmm output register) and
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// VPCMPEQBZ128rm (k register output register).
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bool ArgFolded = false;
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unsigned MemOutSize = MemRec->getValueAsDag("OutOperandList")->getNumArgs();
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unsigned RegOutSize = RegRec->getValueAsDag("OutOperandList")->getNumArgs();
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unsigned MemInSize = MemRec->getValueAsDag("InOperandList")->getNumArgs();
|
|
unsigned RegInSize = RegRec->getValueAsDag("InOperandList")->getNumArgs();
|
|
|
|
// Instructions with one output in their memory form use the memory folded
|
|
// operand as source and destination (Read-Modify-Write).
|
|
unsigned RegStartIdx =
|
|
(MemOutSize + 1 == RegOutSize) && (MemInSize == RegInSize) ? 1 : 0;
|
|
|
|
for (unsigned i = 0, e = MemInst->Operands.size(); i < e; i++) {
|
|
Record *MemOpRec = MemInst->Operands[i].Rec;
|
|
Record *RegOpRec = RegInst->Operands[i + RegStartIdx].Rec;
|
|
|
|
if (MemOpRec == RegOpRec)
|
|
continue;
|
|
|
|
if (isRegisterOperand(MemOpRec) && isRegisterOperand(RegOpRec)) {
|
|
if (getRegOperandSize(MemOpRec) != getRegOperandSize(RegOpRec) ||
|
|
isNOREXRegClass(MemOpRec) != isNOREXRegClass(RegOpRec))
|
|
return false;
|
|
} else if (isMemoryOperand(MemOpRec) && isMemoryOperand(RegOpRec)) {
|
|
if (getMemOperandSize(MemOpRec) != getMemOperandSize(RegOpRec))
|
|
return false;
|
|
} else if (isImmediateOperand(MemOpRec) && isImmediateOperand(RegOpRec)) {
|
|
if (MemOpRec->getValueAsDef("Type") != RegOpRec->getValueAsDef("Type"))
|
|
return false;
|
|
} else {
|
|
// Only one operand can be folded.
|
|
if (ArgFolded)
|
|
return false;
|
|
|
|
assert(isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec));
|
|
ArgFolded = true;
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
private:
|
|
// Return true of the 2 given forms are the opposite of each other.
|
|
bool areOppositeForms(const BitsInit *RegFormBits,
|
|
const BitsInit *MemFormBits) {
|
|
uint64_t MemFormNum = getValueFromBitsInit(MemFormBits);
|
|
uint64_t RegFormNum = getValueFromBitsInit(RegFormBits);
|
|
|
|
if ((MemFormNum == X86Local::MRM0m && RegFormNum == X86Local::MRM0r) ||
|
|
(MemFormNum == X86Local::MRM1m && RegFormNum == X86Local::MRM1r) ||
|
|
(MemFormNum == X86Local::MRM2m && RegFormNum == X86Local::MRM2r) ||
|
|
(MemFormNum == X86Local::MRM3m && RegFormNum == X86Local::MRM3r) ||
|
|
(MemFormNum == X86Local::MRM4m && RegFormNum == X86Local::MRM4r) ||
|
|
(MemFormNum == X86Local::MRM5m && RegFormNum == X86Local::MRM5r) ||
|
|
(MemFormNum == X86Local::MRM6m && RegFormNum == X86Local::MRM6r) ||
|
|
(MemFormNum == X86Local::MRM7m && RegFormNum == X86Local::MRM7r) ||
|
|
(MemFormNum == X86Local::MRMXm && RegFormNum == X86Local::MRMXr) ||
|
|
(MemFormNum == X86Local::MRMDestMem &&
|
|
RegFormNum == X86Local::MRMDestReg) ||
|
|
(MemFormNum == X86Local::MRMSrcMem &&
|
|
RegFormNum == X86Local::MRMSrcReg) ||
|
|
(MemFormNum == X86Local::MRMSrcMem4VOp3 &&
|
|
RegFormNum == X86Local::MRMSrcReg4VOp3) ||
|
|
(MemFormNum == X86Local::MRMSrcMemOp4 &&
|
|
RegFormNum == X86Local::MRMSrcRegOp4))
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
void X86FoldTablesEmitter::addEntryWithFlags(FoldTable &Table,
|
|
const CodeGenInstruction *RegInstr,
|
|
const CodeGenInstruction *MemInstr,
|
|
const UnfoldStrategy S,
|
|
const unsigned int FoldedInd) {
|
|
|
|
X86FoldTableEntry Result = X86FoldTableEntry(RegInstr, MemInstr);
|
|
Record *RegRec = RegInstr->TheDef;
|
|
Record *MemRec = MemInstr->TheDef;
|
|
|
|
// Only table0 entries should explicitly specify a load or store flag.
|
|
if (&Table == &Table0) {
|
|
unsigned MemInOpsNum = MemRec->getValueAsDag("InOperandList")->getNumArgs();
|
|
unsigned RegInOpsNum = RegRec->getValueAsDag("InOperandList")->getNumArgs();
|
|
// If the instruction writes to the folded operand, it will appear as an
|
|
// output in the register form instruction and as an input in the memory
|
|
// form instruction.
|
|
// If the instruction reads from the folded operand, it well appear as in
|
|
// input in both forms.
|
|
if (MemInOpsNum == RegInOpsNum)
|
|
Result.IsLoad = true;
|
|
else
|
|
Result.IsStore = true;
|
|
}
|
|
|
|
Record *RegOpRec = RegInstr->Operands[FoldedInd].Rec;
|
|
Record *MemOpRec = MemInstr->Operands[FoldedInd].Rec;
|
|
|
|
// Unfolding code generates a load/store instruction according to the size of
|
|
// the register in the register form instruction.
|
|
// If the register's size is greater than the memory's operand size, do not
|
|
// allow unfolding.
|
|
if (S == UNFOLD)
|
|
Result.CannotUnfold = false;
|
|
else if (S == NO_UNFOLD)
|
|
Result.CannotUnfold = true;
|
|
else if (getRegOperandSize(RegOpRec) > getMemOperandSize(MemOpRec))
|
|
Result.CannotUnfold = true; // S == NO_STRATEGY
|
|
|
|
uint64_t Enc = getValueFromBitsInit(RegRec->getValueAsBitsInit("OpEncBits"));
|
|
if (isExplicitAlign(RegInstr)) {
|
|
// The instruction require explicitly aligned memory.
|
|
BitsInit *VectSize = RegRec->getValueAsBitsInit("VectSize");
|
|
uint64_t Value = getValueFromBitsInit(VectSize);
|
|
Result.IsAligned = true;
|
|
Result.Alignment = Value;
|
|
} else if (Enc != X86Local::XOP && Enc != X86Local::VEX &&
|
|
Enc != X86Local::EVEX) {
|
|
// Instructions with VEX encoding do not require alignment.
|
|
if (!isExplicitUnalign(RegInstr) && getMemOperandSize(MemOpRec) > 64) {
|
|
// SSE packed vector instructions require a 16 byte alignment.
|
|
Result.IsAligned = true;
|
|
Result.Alignment = 16;
|
|
}
|
|
}
|
|
|
|
Table.push_back(Result);
|
|
}
|
|
|
|
void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr,
|
|
const CodeGenInstruction *MemInstr,
|
|
const UnfoldStrategy S) {
|
|
|
|
Record *RegRec = RegInstr->TheDef;
|
|
Record *MemRec = MemInstr->TheDef;
|
|
unsigned MemOutSize = MemRec->getValueAsDag("OutOperandList")->getNumArgs();
|
|
unsigned RegOutSize = RegRec->getValueAsDag("OutOperandList")->getNumArgs();
|
|
unsigned MemInSize = MemRec->getValueAsDag("InOperandList")->getNumArgs();
|
|
unsigned RegInSize = RegRec->getValueAsDag("InOperandList")->getNumArgs();
|
|
|
|
// Instructions which have the WriteRMW value (Read-Modify-Write) should be
|
|
// added to Table2Addr.
|
|
if (hasDefInList(MemRec, "SchedRW", "WriteRMW") && MemOutSize != RegOutSize &&
|
|
MemInSize == RegInSize) {
|
|
addEntryWithFlags(Table2Addr, RegInstr, MemInstr, S, 0);
|
|
return;
|
|
}
|
|
|
|
if (MemInSize == RegInSize && MemOutSize == RegOutSize) {
|
|
// Load-Folding cases.
|
|
// If the i'th register form operand is a register and the i'th memory form
|
|
// operand is a memory operand, add instructions to Table#i.
|
|
for (unsigned i = RegOutSize, e = RegInstr->Operands.size(); i < e; i++) {
|
|
Record *RegOpRec = RegInstr->Operands[i].Rec;
|
|
Record *MemOpRec = MemInstr->Operands[i].Rec;
|
|
if (isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec)) {
|
|
switch (i) {
|
|
default: llvm_unreachable("Unexpected operand count!");
|
|
case 0:
|
|
addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0);
|
|
return;
|
|
case 1:
|
|
addEntryWithFlags(Table1, RegInstr, MemInstr, S, 1);
|
|
return;
|
|
case 2:
|
|
addEntryWithFlags(Table2, RegInstr, MemInstr, S, 2);
|
|
return;
|
|
case 3:
|
|
addEntryWithFlags(Table3, RegInstr, MemInstr, S, 3);
|
|
return;
|
|
case 4:
|
|
addEntryWithFlags(Table4, RegInstr, MemInstr, S, 4);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
} else if (MemInSize == RegInSize + 1 && MemOutSize + 1 == RegOutSize) {
|
|
// Store-Folding cases.
|
|
// If the memory form instruction performs performs a store, the *output*
|
|
// register of the register form instructions disappear and instead a
|
|
// memory *input* operand appears in the memory form instruction.
|
|
// For example:
|
|
// MOVAPSrr => (outs VR128:$dst), (ins VR128:$src)
|
|
// MOVAPSmr => (outs), (ins f128mem:$dst, VR128:$src)
|
|
Record *RegOpRec = RegInstr->Operands[RegOutSize - 1].Rec;
|
|
Record *MemOpRec = MemInstr->Operands[RegOutSize - 1].Rec;
|
|
if (isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec))
|
|
addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
void X86FoldTablesEmitter::run(raw_ostream &OS) {
|
|
emitSourceFileHeader("X86 fold tables", OS);
|
|
|
|
// Holds all memory instructions
|
|
std::vector<const CodeGenInstruction *> MemInsts;
|
|
// Holds all register instructions - divided according to opcode.
|
|
std::map<uint8_t, std::vector<const CodeGenInstruction *>> RegInsts;
|
|
|
|
ArrayRef<const CodeGenInstruction *> NumberedInstructions =
|
|
Target.getInstructionsByEnumValue();
|
|
|
|
for (const CodeGenInstruction *Inst : NumberedInstructions) {
|
|
if (!Inst->TheDef->getNameInit() || !Inst->TheDef->isSubClassOf("X86Inst"))
|
|
continue;
|
|
|
|
const Record *Rec = Inst->TheDef;
|
|
|
|
// - Do not proceed matching if the instruction in NoFoldSet.
|
|
// - Instructions including RST register class operands are not relevant
|
|
// for memory folding (for further details check the explanation in
|
|
// lib/Target/X86/X86InstrFPStack.td file).
|
|
// - Some instructions (listed in the manual map above) use the register
|
|
// class ptr_rc_tailcall, which can be of a size 32 or 64, to ensure
|
|
// safe mapping of these instruction we manually map them and exclude
|
|
// them from the automation.
|
|
if (find(NoFoldSet, Rec->getName()) != std::end(NoFoldSet) ||
|
|
hasRSTRegClass(Inst) || hasPtrTailcallRegClass(Inst))
|
|
continue;
|
|
|
|
// Add all the memory form instructions to MemInsts, and all the register
|
|
// form instructions to RegInsts[Opc], where Opc in the opcode of each
|
|
// instructions. this helps reducing the runtime of the backend.
|
|
if (hasMemoryFormat(Rec))
|
|
MemInsts.push_back(Inst);
|
|
else if (hasRegisterFormat(Rec)) {
|
|
uint8_t Opc = getValueFromBitsInit(Rec->getValueAsBitsInit("Opcode"));
|
|
RegInsts[Opc].push_back(Inst);
|
|
}
|
|
}
|
|
|
|
// For each memory form instruction, try to find its register form
|
|
// instruction.
|
|
for (const CodeGenInstruction *MemInst : MemInsts) {
|
|
uint8_t Opc =
|
|
getValueFromBitsInit(MemInst->TheDef->getValueAsBitsInit("Opcode"));
|
|
|
|
if (RegInsts.count(Opc) == 0)
|
|
continue;
|
|
|
|
// Two forms (memory & register) of the same instruction must have the same
|
|
// opcode. try matching only with register form instructions with the same
|
|
// opcode.
|
|
std::vector<const CodeGenInstruction *> &OpcRegInsts =
|
|
RegInsts.find(Opc)->second;
|
|
|
|
auto Match = find_if(OpcRegInsts, IsMatch(MemInst, Records));
|
|
if (Match != OpcRegInsts.end()) {
|
|
const CodeGenInstruction *RegInst = *Match;
|
|
// If the matched instruction has it's "FoldGenRegForm" set, map the
|
|
// memory form instruction to the register form instruction pointed by
|
|
// this field
|
|
if (RegInst->TheDef->isValueUnset("FoldGenRegForm")) {
|
|
updateTables(RegInst, MemInst);
|
|
} else {
|
|
const CodeGenInstruction *AltRegInst =
|
|
getAltRegInst(RegInst, Records, Target);
|
|
updateTables(AltRegInst, MemInst);
|
|
}
|
|
OpcRegInsts.erase(Match);
|
|
}
|
|
}
|
|
|
|
// Add the manually mapped instructions listed above.
|
|
for (const ManualMapEntry &Entry : ManualMapSet) {
|
|
Record *RegInstIter = Records.getDef(Entry.RegInstStr);
|
|
Record *MemInstIter = Records.getDef(Entry.MemInstStr);
|
|
|
|
updateTables(&(Target.getInstruction(RegInstIter)),
|
|
&(Target.getInstruction(MemInstIter)), Entry.Strategy);
|
|
}
|
|
|
|
// Print all tables to raw_ostream OS.
|
|
printTable(Table2Addr, "Table2Addr", OS);
|
|
printTable(Table0, "Table0", OS);
|
|
printTable(Table1, "Table1", OS);
|
|
printTable(Table2, "Table2", OS);
|
|
printTable(Table3, "Table3", OS);
|
|
printTable(Table4, "Table4", OS);
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void EmitX86FoldTables(RecordKeeper &RK, raw_ostream &OS) {
|
|
X86FoldTablesEmitter(RK).run(OS);
|
|
}
|
|
} // namespace llvm
|