eb811915d2
30-bit like the reset of the controllers supported by this driver. Actually ALi M5451 can be setup up to generate 32-bit addresses by setting the 31st bit via the accompanying ISA bridge, which allows it to work in sparc64 machines whose IOMMU require at least 32-bit DMA. Even though other architectures would also benefit from 32-bit DMA, enabling this bit is limited to sparc64 as bus_dma(9) doesn't generally guarantee that a low address of BUS_SPACE_MAXADDR_32BIT results in a buffer in the 32-bit range. - According to Tatsuo YOKOGAWA's ali(4), the the DMA transfer size of ALi M5451 is fixed to 64k and in fact using the default size of 4k - The 4DWAVE DX and NX require the recording buffer to be 8-byte aligned so adjust the bus_dma_tag_create(9) accordingly. - Unlike the rest of the controllers supported by this driver, the ALi M5451 only has 32 hardware channels instead of 64 so limit the loop in tr_intr() accordingly. [1] Submitted by: yongari [1] Reviewed by: yongari (superset of what is committed) MFC after: 3 days
1071 lines
25 KiB
C
1071 lines
25 KiB
C
/*-
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* Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifdef HAVE_KERNEL_OPTION_HEADERS
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#include "opt_snd.h"
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#endif
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/pcm/ac97.h>
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#include <dev/sound/pci/t4dwave.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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SND_DECLARE_FILE("$FreeBSD$");
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/* -------------------------------------------------------------------- */
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#define TDX_PCI_ID 0x20001023
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#define TNX_PCI_ID 0x20011023
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#define ALI_PCI_ID 0x545110b9
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#define SPA_PCI_ID 0x70181039
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#define TR_DEFAULT_BUFSZ 0x1000
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/* For ALi M5451 the DMA transfer size appears to be fixed to 64k. */
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#define ALI_BUFSZ 0x10000
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#define TR_BUFALGN 0x8
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#define TR_TIMEOUT_CDC 0xffff
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#define TR_MAXHWCH 64
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#define ALI_MAXHWCH 32
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#define TR_MAXPLAYCH 4
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#define ALI_MAXPLAYCH 1
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/*
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* Though, it's not clearly documented in the 4DWAVE datasheet, the
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* DX and NX chips can't handle DMA addresses located above 1GB as the
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* LBA (loop begin address) register which holds the DMA base address
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* is 32-bit, but the two MSBs are used for other purposes.
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*/
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#define TR_MAXADDR ((1U << 30) - 1)
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#define ALI_MAXADDR ((1U << 31) - 1)
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struct tr_info;
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/* channel registers */
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struct tr_chinfo {
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u_int32_t cso, alpha, fms, fmc, ec;
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u_int32_t lba;
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u_int32_t eso, delta;
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u_int32_t rvol, cvol;
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u_int32_t gvsel, pan, vol, ctrl;
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u_int32_t active:1, was_active:1;
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int index, bufhalf;
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struct snd_dbuf *buffer;
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struct pcm_channel *channel;
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struct tr_info *parent;
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};
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struct tr_rchinfo {
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u_int32_t delta;
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u_int32_t active:1, was_active:1;
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struct snd_dbuf *buffer;
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struct pcm_channel *channel;
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struct tr_info *parent;
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};
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/* device private data */
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struct tr_info {
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u_int32_t type;
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u_int32_t rev;
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bus_space_tag_t st;
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bus_space_handle_t sh;
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bus_dma_tag_t parent_dmat;
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struct resource *reg, *irq;
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int regtype, regid, irqid;
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void *ih;
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struct mtx *lock;
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u_int32_t hwchns;
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u_int32_t playchns;
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unsigned int bufsz;
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struct tr_chinfo chinfo[TR_MAXPLAYCH];
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struct tr_rchinfo recchinfo;
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};
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/* -------------------------------------------------------------------- */
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static u_int32_t tr_recfmt[] = {
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SND_FORMAT(AFMT_U8, 1, 0),
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SND_FORMAT(AFMT_U8, 2, 0),
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SND_FORMAT(AFMT_S8, 1, 0),
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SND_FORMAT(AFMT_S8, 2, 0),
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SND_FORMAT(AFMT_S16_LE, 1, 0),
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SND_FORMAT(AFMT_S16_LE, 2, 0),
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SND_FORMAT(AFMT_U16_LE, 1, 0),
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SND_FORMAT(AFMT_U16_LE, 2, 0),
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0
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};
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static struct pcmchan_caps tr_reccaps = {4000, 48000, tr_recfmt, 0};
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static u_int32_t tr_playfmt[] = {
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SND_FORMAT(AFMT_U8, 1, 0),
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SND_FORMAT(AFMT_U8, 2, 0),
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SND_FORMAT(AFMT_S8, 1, 0),
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SND_FORMAT(AFMT_S8, 2, 0),
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SND_FORMAT(AFMT_S16_LE, 1, 0),
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SND_FORMAT(AFMT_S16_LE, 2, 0),
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SND_FORMAT(AFMT_U16_LE, 1, 0),
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SND_FORMAT(AFMT_U16_LE, 2, 0),
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0
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};
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static struct pcmchan_caps tr_playcaps = {4000, 48000, tr_playfmt, 0};
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/* -------------------------------------------------------------------- */
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/* Hardware */
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static u_int32_t
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tr_rd(struct tr_info *tr, int regno, int size)
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{
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switch(size) {
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case 1:
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return bus_space_read_1(tr->st, tr->sh, regno);
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case 2:
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return bus_space_read_2(tr->st, tr->sh, regno);
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case 4:
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return bus_space_read_4(tr->st, tr->sh, regno);
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default:
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return 0xffffffff;
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}
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}
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static void
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tr_wr(struct tr_info *tr, int regno, u_int32_t data, int size)
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{
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switch(size) {
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case 1:
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bus_space_write_1(tr->st, tr->sh, regno, data);
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break;
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case 2:
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bus_space_write_2(tr->st, tr->sh, regno, data);
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break;
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case 4:
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bus_space_write_4(tr->st, tr->sh, regno, data);
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break;
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}
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}
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/* -------------------------------------------------------------------- */
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/* ac97 codec */
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static int
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tr_rdcd(kobj_t obj, void *devinfo, int regno)
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{
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struct tr_info *tr = (struct tr_info *)devinfo;
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int i, j, treg, trw;
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switch (tr->type) {
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case SPA_PCI_ID:
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treg=SPA_REG_CODECRD;
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trw=SPA_CDC_RWSTAT;
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break;
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case ALI_PCI_ID:
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if (tr->rev > 0x01)
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treg=TDX_REG_CODECWR;
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else
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treg=TDX_REG_CODECRD;
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trw=TDX_CDC_RWSTAT;
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break;
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case TDX_PCI_ID:
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treg=TDX_REG_CODECRD;
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trw=TDX_CDC_RWSTAT;
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break;
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case TNX_PCI_ID:
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treg=(regno & 0x100)? TNX_REG_CODEC2RD : TNX_REG_CODEC1RD;
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trw=TNX_CDC_RWSTAT;
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break;
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default:
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printf("!!! tr_rdcd defaulted !!!\n");
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return -1;
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}
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i = j = 0;
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regno &= 0x7f;
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snd_mtxlock(tr->lock);
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if (tr->type == ALI_PCI_ID) {
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u_int32_t chk1, chk2;
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j = trw;
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for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
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j = tr_rd(tr, treg, 4);
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if (i > 0) {
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chk1 = tr_rd(tr, 0xc8, 4);
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chk2 = tr_rd(tr, 0xc8, 4);
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for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
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i--)
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chk2 = tr_rd(tr, 0xc8, 4);
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}
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}
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if (tr->type != ALI_PCI_ID || i > 0) {
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tr_wr(tr, treg, regno | trw, 4);
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j=trw;
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for (i=TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
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j=tr_rd(tr, treg, 4);
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}
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snd_mtxunlock(tr->lock);
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if (i == 0) printf("codec timeout during read of register %x\n", regno);
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return (j >> TR_CDC_DATA) & 0xffff;
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}
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static int
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tr_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
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{
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struct tr_info *tr = (struct tr_info *)devinfo;
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int i, j, treg, trw;
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switch (tr->type) {
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case SPA_PCI_ID:
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treg=SPA_REG_CODECWR;
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trw=SPA_CDC_RWSTAT;
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break;
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case ALI_PCI_ID:
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case TDX_PCI_ID:
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treg=TDX_REG_CODECWR;
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trw=TDX_CDC_RWSTAT;
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break;
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case TNX_PCI_ID:
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treg=TNX_REG_CODECWR;
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trw=TNX_CDC_RWSTAT | ((regno & 0x100)? TNX_CDC_SEC : 0);
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break;
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default:
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printf("!!! tr_wrcd defaulted !!!");
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return -1;
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}
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i = 0;
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regno &= 0x7f;
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#if 0
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printf("tr_wrcd: reg %x was %x", regno, tr_rdcd(devinfo, regno));
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#endif
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j=trw;
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snd_mtxlock(tr->lock);
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if (tr->type == ALI_PCI_ID) {
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j = trw;
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for (i = TR_TIMEOUT_CDC; (i > 0) && (j & trw); i--)
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j = tr_rd(tr, treg, 4);
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if (i > 0) {
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u_int32_t chk1, chk2;
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chk1 = tr_rd(tr, 0xc8, 4);
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chk2 = tr_rd(tr, 0xc8, 4);
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for (i = TR_TIMEOUT_CDC; (i > 0) && (chk1 == chk2);
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i--)
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chk2 = tr_rd(tr, 0xc8, 4);
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}
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}
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if (tr->type != ALI_PCI_ID || i > 0) {
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for (i=TR_TIMEOUT_CDC; (i>0) && (j & trw); i--)
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j=tr_rd(tr, treg, 4);
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if (tr->type == ALI_PCI_ID && tr->rev > 0x01)
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trw |= 0x0100;
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tr_wr(tr, treg, (data << TR_CDC_DATA) | regno | trw, 4);
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}
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#if 0
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printf(" - wrote %x, now %x\n", data, tr_rdcd(devinfo, regno));
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#endif
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snd_mtxunlock(tr->lock);
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if (i==0) printf("codec timeout writing %x, data %x\n", regno, data);
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return (i > 0)? 0 : -1;
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}
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static kobj_method_t tr_ac97_methods[] = {
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KOBJMETHOD(ac97_read, tr_rdcd),
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KOBJMETHOD(ac97_write, tr_wrcd),
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KOBJMETHOD_END
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};
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AC97_DECLARE(tr_ac97);
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/* -------------------------------------------------------------------- */
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/* playback channel interrupts */
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#if 0
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static u_int32_t
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tr_testint(struct tr_chinfo *ch)
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{
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struct tr_info *tr = ch->parent;
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int bank, chan;
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bank = (ch->index & 0x20) ? 1 : 0;
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chan = ch->index & 0x1f;
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return tr_rd(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 4) & (1 << chan);
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}
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#endif
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static void
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tr_clrint(struct tr_chinfo *ch)
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{
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struct tr_info *tr = ch->parent;
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int bank, chan;
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bank = (ch->index & 0x20) ? 1 : 0;
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chan = ch->index & 0x1f;
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tr_wr(tr, bank? TR_REG_ADDRINTB : TR_REG_ADDRINTA, 1 << chan, 4);
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}
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static void
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tr_enaint(struct tr_chinfo *ch, int enable)
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{
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struct tr_info *tr = ch->parent;
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u_int32_t i, reg;
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int bank, chan;
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snd_mtxlock(tr->lock);
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bank = (ch->index & 0x20) ? 1 : 0;
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chan = ch->index & 0x1f;
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reg = bank? TR_REG_INTENB : TR_REG_INTENA;
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i = tr_rd(tr, reg, 4);
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i &= ~(1 << chan);
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i |= (enable? 1 : 0) << chan;
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tr_clrint(ch);
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tr_wr(tr, reg, i, 4);
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snd_mtxunlock(tr->lock);
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}
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/* playback channels */
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static void
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tr_selch(struct tr_chinfo *ch)
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{
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struct tr_info *tr = ch->parent;
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int i;
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i = tr_rd(tr, TR_REG_CIR, 4);
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i &= ~TR_CIR_MASK;
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i |= ch->index & 0x3f;
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tr_wr(tr, TR_REG_CIR, i, 4);
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}
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static void
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tr_startch(struct tr_chinfo *ch)
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{
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struct tr_info *tr = ch->parent;
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int bank, chan;
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bank = (ch->index & 0x20) ? 1 : 0;
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chan = ch->index & 0x1f;
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tr_wr(tr, bank? TR_REG_STARTB : TR_REG_STARTA, 1 << chan, 4);
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}
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static void
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tr_stopch(struct tr_chinfo *ch)
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{
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struct tr_info *tr = ch->parent;
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int bank, chan;
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bank = (ch->index & 0x20) ? 1 : 0;
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chan = ch->index & 0x1f;
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tr_wr(tr, bank? TR_REG_STOPB : TR_REG_STOPA, 1 << chan, 4);
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}
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static void
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tr_wrch(struct tr_chinfo *ch)
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{
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struct tr_info *tr = ch->parent;
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u_int32_t cr[TR_CHN_REGS], i;
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ch->gvsel &= 0x00000001;
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ch->fmc &= 0x00000003;
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ch->fms &= 0x0000000f;
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ch->ctrl &= 0x0000000f;
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ch->pan &= 0x0000007f;
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ch->rvol &= 0x0000007f;
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ch->cvol &= 0x0000007f;
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ch->vol &= 0x000000ff;
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ch->ec &= 0x00000fff;
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ch->alpha &= 0x00000fff;
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ch->delta &= 0x0000ffff;
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if (tr->type == ALI_PCI_ID)
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ch->lba &= ALI_MAXADDR;
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else
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ch->lba &= TR_MAXADDR;
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|
|
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cr[1]=ch->lba;
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cr[3]=(ch->fmc<<14) | (ch->rvol<<7) | (ch->cvol);
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cr[4]=(ch->gvsel<<31) | (ch->pan<<24) | (ch->vol<<16) | (ch->ctrl<<12) | (ch->ec);
|
|
|
|
switch (tr->type) {
|
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case SPA_PCI_ID:
|
|
case ALI_PCI_ID:
|
|
case TDX_PCI_ID:
|
|
ch->cso &= 0x0000ffff;
|
|
ch->eso &= 0x0000ffff;
|
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cr[0]=(ch->cso<<16) | (ch->alpha<<4) | (ch->fms);
|
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cr[2]=(ch->eso<<16) | (ch->delta);
|
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break;
|
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case TNX_PCI_ID:
|
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ch->cso &= 0x00ffffff;
|
|
ch->eso &= 0x00ffffff;
|
|
cr[0]=((ch->delta & 0xff)<<24) | (ch->cso);
|
|
cr[2]=((ch->delta>>8)<<24) | (ch->eso);
|
|
cr[3]|=(ch->alpha<<20) | (ch->fms<<16) | (ch->fmc<<14);
|
|
break;
|
|
}
|
|
snd_mtxlock(tr->lock);
|
|
tr_selch(ch);
|
|
for (i=0; i<TR_CHN_REGS; i++)
|
|
tr_wr(tr, TR_REG_CHNBASE+(i<<2), cr[i], 4);
|
|
snd_mtxunlock(tr->lock);
|
|
}
|
|
|
|
static void
|
|
tr_rdch(struct tr_chinfo *ch)
|
|
{
|
|
struct tr_info *tr = ch->parent;
|
|
u_int32_t cr[5], i;
|
|
|
|
snd_mtxlock(tr->lock);
|
|
tr_selch(ch);
|
|
for (i=0; i<5; i++)
|
|
cr[i]=tr_rd(tr, TR_REG_CHNBASE+(i<<2), 4);
|
|
snd_mtxunlock(tr->lock);
|
|
|
|
|
|
if (tr->type == ALI_PCI_ID)
|
|
ch->lba=(cr[1] & ALI_MAXADDR);
|
|
else
|
|
ch->lba=(cr[1] & TR_MAXADDR);
|
|
ch->fmc= (cr[3] & 0x0000c000) >> 14;
|
|
ch->rvol= (cr[3] & 0x00003f80) >> 7;
|
|
ch->cvol= (cr[3] & 0x0000007f);
|
|
ch->gvsel= (cr[4] & 0x80000000) >> 31;
|
|
ch->pan= (cr[4] & 0x7f000000) >> 24;
|
|
ch->vol= (cr[4] & 0x00ff0000) >> 16;
|
|
ch->ctrl= (cr[4] & 0x0000f000) >> 12;
|
|
ch->ec= (cr[4] & 0x00000fff);
|
|
switch(tr->type) {
|
|
case SPA_PCI_ID:
|
|
case ALI_PCI_ID:
|
|
case TDX_PCI_ID:
|
|
ch->cso= (cr[0] & 0xffff0000) >> 16;
|
|
ch->alpha= (cr[0] & 0x0000fff0) >> 4;
|
|
ch->fms= (cr[0] & 0x0000000f);
|
|
ch->eso= (cr[2] & 0xffff0000) >> 16;
|
|
ch->delta= (cr[2] & 0x0000ffff);
|
|
break;
|
|
case TNX_PCI_ID:
|
|
ch->cso= (cr[0] & 0x00ffffff);
|
|
ch->eso= (cr[2] & 0x00ffffff);
|
|
ch->delta= ((cr[2] & 0xff000000) >> 16) | ((cr[0] & 0xff000000) >> 24);
|
|
ch->alpha= (cr[3] & 0xfff00000) >> 20;
|
|
ch->fms= (cr[3] & 0x000f0000) >> 16;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static u_int32_t
|
|
tr_fmttobits(u_int32_t fmt)
|
|
{
|
|
u_int32_t bits;
|
|
|
|
bits = 0;
|
|
bits |= (fmt & AFMT_SIGNED)? 0x2 : 0;
|
|
bits |= (AFMT_CHANNEL(fmt) > 1)? 0x4 : 0;
|
|
bits |= (fmt & AFMT_16BIT)? 0x8 : 0;
|
|
|
|
return bits;
|
|
}
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/* channel interface */
|
|
|
|
static void *
|
|
trpchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
|
|
{
|
|
struct tr_info *tr = devinfo;
|
|
struct tr_chinfo *ch;
|
|
|
|
KASSERT(dir == PCMDIR_PLAY, ("trpchan_init: bad direction"));
|
|
ch = &tr->chinfo[tr->playchns];
|
|
ch->index = tr->playchns++;
|
|
ch->buffer = b;
|
|
ch->parent = tr;
|
|
ch->channel = c;
|
|
if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
|
|
return NULL;
|
|
|
|
return ch;
|
|
}
|
|
|
|
static int
|
|
trpchan_setformat(kobj_t obj, void *data, u_int32_t format)
|
|
{
|
|
struct tr_chinfo *ch = data;
|
|
|
|
ch->ctrl = tr_fmttobits(format) | 0x01;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u_int32_t
|
|
trpchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
|
|
{
|
|
struct tr_chinfo *ch = data;
|
|
|
|
ch->delta = (speed << 12) / 48000;
|
|
return (ch->delta * 48000) >> 12;
|
|
}
|
|
|
|
static u_int32_t
|
|
trpchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
|
|
{
|
|
struct tr_chinfo *ch = data;
|
|
|
|
sndbuf_resize(ch->buffer, 2, blocksize);
|
|
return blocksize;
|
|
}
|
|
|
|
static int
|
|
trpchan_trigger(kobj_t obj, void *data, int go)
|
|
{
|
|
struct tr_chinfo *ch = data;
|
|
|
|
if (!PCMTRIG_COMMON(go))
|
|
return 0;
|
|
|
|
if (go == PCMTRIG_START) {
|
|
ch->fmc = 3;
|
|
ch->fms = 0;
|
|
ch->ec = 0;
|
|
ch->alpha = 0;
|
|
ch->lba = sndbuf_getbufaddr(ch->buffer);
|
|
ch->cso = 0;
|
|
ch->eso = (sndbuf_getsize(ch->buffer) / sndbuf_getalign(ch->buffer)) - 1;
|
|
ch->rvol = ch->cvol = 0x7f;
|
|
ch->gvsel = 0;
|
|
ch->pan = 0;
|
|
ch->vol = 0;
|
|
ch->bufhalf = 0;
|
|
tr_wrch(ch);
|
|
tr_enaint(ch, 1);
|
|
tr_startch(ch);
|
|
ch->active = 1;
|
|
} else {
|
|
tr_stopch(ch);
|
|
ch->active = 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u_int32_t
|
|
trpchan_getptr(kobj_t obj, void *data)
|
|
{
|
|
struct tr_chinfo *ch = data;
|
|
|
|
tr_rdch(ch);
|
|
return ch->cso * sndbuf_getalign(ch->buffer);
|
|
}
|
|
|
|
static struct pcmchan_caps *
|
|
trpchan_getcaps(kobj_t obj, void *data)
|
|
{
|
|
return &tr_playcaps;
|
|
}
|
|
|
|
static kobj_method_t trpchan_methods[] = {
|
|
KOBJMETHOD(channel_init, trpchan_init),
|
|
KOBJMETHOD(channel_setformat, trpchan_setformat),
|
|
KOBJMETHOD(channel_setspeed, trpchan_setspeed),
|
|
KOBJMETHOD(channel_setblocksize, trpchan_setblocksize),
|
|
KOBJMETHOD(channel_trigger, trpchan_trigger),
|
|
KOBJMETHOD(channel_getptr, trpchan_getptr),
|
|
KOBJMETHOD(channel_getcaps, trpchan_getcaps),
|
|
KOBJMETHOD_END
|
|
};
|
|
CHANNEL_DECLARE(trpchan);
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/* rec channel interface */
|
|
|
|
static void *
|
|
trrchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
|
|
{
|
|
struct tr_info *tr = devinfo;
|
|
struct tr_rchinfo *ch;
|
|
|
|
KASSERT(dir == PCMDIR_REC, ("trrchan_init: bad direction"));
|
|
ch = &tr->recchinfo;
|
|
ch->buffer = b;
|
|
ch->parent = tr;
|
|
ch->channel = c;
|
|
if (sndbuf_alloc(ch->buffer, tr->parent_dmat, 0, tr->bufsz) != 0)
|
|
return NULL;
|
|
|
|
return ch;
|
|
}
|
|
|
|
static int
|
|
trrchan_setformat(kobj_t obj, void *data, u_int32_t format)
|
|
{
|
|
struct tr_rchinfo *ch = data;
|
|
struct tr_info *tr = ch->parent;
|
|
u_int32_t i, bits;
|
|
|
|
bits = tr_fmttobits(format);
|
|
/* set # of samples between interrupts */
|
|
i = (sndbuf_runsz(ch->buffer) >> ((bits & 0x08)? 1 : 0)) - 1;
|
|
tr_wr(tr, TR_REG_SBBL, i | (i << 16), 4);
|
|
/* set sample format */
|
|
i = 0x18 | (bits << 4);
|
|
tr_wr(tr, TR_REG_SBCTRL, i, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u_int32_t
|
|
trrchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
|
|
{
|
|
struct tr_rchinfo *ch = data;
|
|
struct tr_info *tr = ch->parent;
|
|
|
|
/* setup speed */
|
|
ch->delta = (48000 << 12) / speed;
|
|
tr_wr(tr, TR_REG_SBDELTA, ch->delta, 2);
|
|
|
|
/* return closest possible speed */
|
|
return (48000 << 12) / ch->delta;
|
|
}
|
|
|
|
static u_int32_t
|
|
trrchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
|
|
{
|
|
struct tr_rchinfo *ch = data;
|
|
|
|
sndbuf_resize(ch->buffer, 2, blocksize);
|
|
|
|
return blocksize;
|
|
}
|
|
|
|
static int
|
|
trrchan_trigger(kobj_t obj, void *data, int go)
|
|
{
|
|
struct tr_rchinfo *ch = data;
|
|
struct tr_info *tr = ch->parent;
|
|
u_int32_t i;
|
|
|
|
if (!PCMTRIG_COMMON(go))
|
|
return 0;
|
|
|
|
if (go == PCMTRIG_START) {
|
|
/* set up dma mode regs */
|
|
tr_wr(tr, TR_REG_DMAR15, 0, 1);
|
|
i = tr_rd(tr, TR_REG_DMAR11, 1) & 0x03;
|
|
tr_wr(tr, TR_REG_DMAR11, i | 0x54, 1);
|
|
/* set up base address */
|
|
tr_wr(tr, TR_REG_DMAR0, sndbuf_getbufaddr(ch->buffer), 4);
|
|
/* set up buffer size */
|
|
i = tr_rd(tr, TR_REG_DMAR4, 4) & ~0x00ffffff;
|
|
tr_wr(tr, TR_REG_DMAR4, i | (sndbuf_runsz(ch->buffer) - 1), 4);
|
|
/* start */
|
|
tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) | 1, 1);
|
|
ch->active = 1;
|
|
} else {
|
|
tr_wr(tr, TR_REG_SBCTRL, tr_rd(tr, TR_REG_SBCTRL, 1) & ~7, 1);
|
|
ch->active = 0;
|
|
}
|
|
|
|
/* return 0 if ok */
|
|
return 0;
|
|
}
|
|
|
|
static u_int32_t
|
|
trrchan_getptr(kobj_t obj, void *data)
|
|
{
|
|
struct tr_rchinfo *ch = data;
|
|
struct tr_info *tr = ch->parent;
|
|
|
|
/* return current byte offset of channel */
|
|
return tr_rd(tr, TR_REG_DMAR0, 4) - sndbuf_getbufaddr(ch->buffer);
|
|
}
|
|
|
|
static struct pcmchan_caps *
|
|
trrchan_getcaps(kobj_t obj, void *data)
|
|
{
|
|
return &tr_reccaps;
|
|
}
|
|
|
|
static kobj_method_t trrchan_methods[] = {
|
|
KOBJMETHOD(channel_init, trrchan_init),
|
|
KOBJMETHOD(channel_setformat, trrchan_setformat),
|
|
KOBJMETHOD(channel_setspeed, trrchan_setspeed),
|
|
KOBJMETHOD(channel_setblocksize, trrchan_setblocksize),
|
|
KOBJMETHOD(channel_trigger, trrchan_trigger),
|
|
KOBJMETHOD(channel_getptr, trrchan_getptr),
|
|
KOBJMETHOD(channel_getcaps, trrchan_getcaps),
|
|
KOBJMETHOD_END
|
|
};
|
|
CHANNEL_DECLARE(trrchan);
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/* The interrupt handler */
|
|
|
|
static void
|
|
tr_intr(void *p)
|
|
{
|
|
struct tr_info *tr = (struct tr_info *)p;
|
|
struct tr_chinfo *ch;
|
|
u_int32_t active, mask, bufhalf, chnum, intsrc;
|
|
int tmp;
|
|
|
|
intsrc = tr_rd(tr, TR_REG_MISCINT, 4);
|
|
if (intsrc & TR_INT_ADDR) {
|
|
chnum = 0;
|
|
while (chnum < tr->hwchns) {
|
|
mask = 0x00000001;
|
|
active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4);
|
|
bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4);
|
|
if (active) {
|
|
do {
|
|
if (active & mask) {
|
|
tmp = (bufhalf & mask)? 1 : 0;
|
|
if (chnum < tr->playchns) {
|
|
ch = &tr->chinfo[chnum];
|
|
/* printf("%d @ %d, ", chnum, trpchan_getptr(NULL, ch)); */
|
|
if (ch->bufhalf != tmp) {
|
|
chn_intr(ch->channel);
|
|
ch->bufhalf = tmp;
|
|
}
|
|
}
|
|
}
|
|
chnum++;
|
|
mask <<= 1;
|
|
} while (chnum & 31);
|
|
} else
|
|
chnum += 32;
|
|
|
|
tr_wr(tr, (chnum <= 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, active, 4);
|
|
}
|
|
}
|
|
if (intsrc & TR_INT_SB) {
|
|
chn_intr(tr->recchinfo.channel);
|
|
tr_rd(tr, TR_REG_SBR9, 1);
|
|
tr_rd(tr, TR_REG_SBR10, 1);
|
|
}
|
|
}
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
|
|
/*
|
|
* Probe and attach the card
|
|
*/
|
|
|
|
static int
|
|
tr_init(struct tr_info *tr)
|
|
{
|
|
switch (tr->type) {
|
|
case SPA_PCI_ID:
|
|
tr_wr(tr, SPA_REG_GPIO, 0, 4);
|
|
tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4);
|
|
break;
|
|
case TDX_PCI_ID:
|
|
tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4);
|
|
break;
|
|
case TNX_PCI_ID:
|
|
tr_wr(tr, TNX_REG_CODECST, TNX_CDC_ON, 4);
|
|
break;
|
|
}
|
|
|
|
tr_wr(tr, TR_REG_CIR, TR_CIR_MIDENA | TR_CIR_ADDRENA, 4);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
tr_pci_probe(device_t dev)
|
|
{
|
|
switch (pci_get_devid(dev)) {
|
|
case SPA_PCI_ID:
|
|
device_set_desc(dev, "SiS 7018");
|
|
return BUS_PROBE_DEFAULT;
|
|
case ALI_PCI_ID:
|
|
device_set_desc(dev, "Acer Labs M5451");
|
|
return BUS_PROBE_DEFAULT;
|
|
case TDX_PCI_ID:
|
|
device_set_desc(dev, "Trident 4DWave DX");
|
|
return BUS_PROBE_DEFAULT;
|
|
case TNX_PCI_ID:
|
|
device_set_desc(dev, "Trident 4DWave NX");
|
|
return BUS_PROBE_DEFAULT;
|
|
}
|
|
|
|
return ENXIO;
|
|
}
|
|
|
|
static int
|
|
tr_pci_attach(device_t dev)
|
|
{
|
|
u_int32_t data;
|
|
struct tr_info *tr;
|
|
struct ac97_info *codec = 0;
|
|
bus_addr_t lowaddr;
|
|
int i, dacn;
|
|
char status[SND_STATUSLEN];
|
|
#ifdef __sparc64__
|
|
device_t *children;
|
|
int nchildren;
|
|
#endif
|
|
|
|
tr = malloc(sizeof(*tr), M_DEVBUF, M_WAITOK | M_ZERO);
|
|
tr->type = pci_get_devid(dev);
|
|
tr->rev = pci_get_revid(dev);
|
|
tr->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_t4dwave softc");
|
|
|
|
if (resource_int_value(device_get_name(dev), device_get_unit(dev),
|
|
"dac", &i) == 0) {
|
|
if (i < 1)
|
|
dacn = 1;
|
|
else if (i > TR_MAXPLAYCH)
|
|
dacn = TR_MAXPLAYCH;
|
|
else
|
|
dacn = i;
|
|
} else {
|
|
switch (tr->type) {
|
|
case ALI_PCI_ID:
|
|
dacn = ALI_MAXPLAYCH;
|
|
break;
|
|
default:
|
|
dacn = TR_MAXPLAYCH;
|
|
break;
|
|
}
|
|
}
|
|
|
|
data = pci_read_config(dev, PCIR_COMMAND, 2);
|
|
data |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
|
|
pci_write_config(dev, PCIR_COMMAND, data, 2);
|
|
data = pci_read_config(dev, PCIR_COMMAND, 2);
|
|
|
|
tr->regid = PCIR_BAR(0);
|
|
tr->regtype = SYS_RES_IOPORT;
|
|
tr->reg = bus_alloc_resource_any(dev, tr->regtype, &tr->regid,
|
|
RF_ACTIVE);
|
|
if (tr->reg) {
|
|
tr->st = rman_get_bustag(tr->reg);
|
|
tr->sh = rman_get_bushandle(tr->reg);
|
|
} else {
|
|
device_printf(dev, "unable to map register space\n");
|
|
goto bad;
|
|
}
|
|
|
|
if (tr_init(tr) == -1) {
|
|
device_printf(dev, "unable to initialize the card\n");
|
|
goto bad;
|
|
}
|
|
tr->playchns = 0;
|
|
|
|
codec = AC97_CREATE(dev, tr, tr_ac97);
|
|
if (codec == NULL) goto bad;
|
|
if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
|
|
|
|
tr->irqid = 0;
|
|
tr->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &tr->irqid,
|
|
RF_ACTIVE | RF_SHAREABLE);
|
|
if (!tr->irq || snd_setup_intr(dev, tr->irq, 0, tr_intr, tr, &tr->ih)) {
|
|
device_printf(dev, "unable to map interrupt\n");
|
|
goto bad;
|
|
}
|
|
|
|
if (tr->type == ALI_PCI_ID) {
|
|
/*
|
|
* The M5451 generates 31 bit of DMA and in order to do
|
|
* 32-bit DMA, the 31st bit can be set via its accompanying
|
|
* ISA bridge. Note that we can't predict whether bus_dma(9)
|
|
* will actually supply us with a 32-bit buffer and even when
|
|
* using a low address of BUS_SPACE_MAXADDR_32BIT for both
|
|
* we might end up with the play buffer being in the 32-bit
|
|
* range while the record buffer isn't or vice versa. So we
|
|
* limit enabling the 31st bit to sparc64, where the IOMMU
|
|
* guarantees that we're using a 32-bit address (and in turn
|
|
* requires it).
|
|
*/
|
|
lowaddr = ALI_MAXADDR;
|
|
#ifdef __sparc64__
|
|
if (device_get_children(device_get_parent(dev), &children,
|
|
&nchildren) == 0) {
|
|
for (i = 0; i < nchildren; i++) {
|
|
if (pci_get_devid(children[i]) == 0x153310b9) {
|
|
lowaddr = BUS_SPACE_MAXADDR_32BIT;
|
|
data = pci_read_config(children[i],
|
|
0x7e, 1);
|
|
if (bootverbose)
|
|
device_printf(dev,
|
|
"M1533 0x7e: 0x%x -> ",
|
|
data);
|
|
data |= 0x1;
|
|
if (bootverbose)
|
|
printf("0x%x\n", data);
|
|
pci_write_config(children[i], 0x7e,
|
|
data, 1);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
free(children, M_TEMP);
|
|
#endif
|
|
tr->hwchns = ALI_MAXHWCH;
|
|
tr->bufsz = ALI_BUFSZ;
|
|
} else {
|
|
lowaddr = TR_MAXADDR;
|
|
tr->hwchns = TR_MAXHWCH;
|
|
tr->bufsz = pcm_getbuffersize(dev, 4096, TR_DEFAULT_BUFSZ,
|
|
65536);
|
|
}
|
|
|
|
if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev),
|
|
/*alignment*/TR_BUFALGN,
|
|
/*boundary*/0,
|
|
/*lowaddr*/lowaddr,
|
|
/*highaddr*/BUS_SPACE_MAXADDR,
|
|
/*filter*/NULL, /*filterarg*/NULL,
|
|
/*maxsize*/tr->bufsz, /*nsegments*/1, /*maxsegz*/tr->bufsz,
|
|
/*flags*/0, /*lockfunc*/busdma_lock_mutex,
|
|
/*lockarg*/&Giant, &tr->parent_dmat) != 0) {
|
|
device_printf(dev, "unable to create dma tag\n");
|
|
goto bad;
|
|
}
|
|
|
|
snprintf(status, 64, "at io 0x%lx irq %ld %s",
|
|
rman_get_start(tr->reg), rman_get_start(tr->irq),PCM_KLDSTRING(snd_t4dwave));
|
|
|
|
if (pcm_register(dev, tr, dacn, 1))
|
|
goto bad;
|
|
pcm_addchan(dev, PCMDIR_REC, &trrchan_class, tr);
|
|
for (i = 0; i < dacn; i++)
|
|
pcm_addchan(dev, PCMDIR_PLAY, &trpchan_class, tr);
|
|
pcm_setstatus(dev, status);
|
|
|
|
return 0;
|
|
|
|
bad:
|
|
if (codec) ac97_destroy(codec);
|
|
if (tr->reg) bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
|
|
if (tr->ih) bus_teardown_intr(dev, tr->irq, tr->ih);
|
|
if (tr->irq) bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
|
|
if (tr->parent_dmat) bus_dma_tag_destroy(tr->parent_dmat);
|
|
if (tr->lock) snd_mtxfree(tr->lock);
|
|
free(tr, M_DEVBUF);
|
|
return ENXIO;
|
|
}
|
|
|
|
static int
|
|
tr_pci_detach(device_t dev)
|
|
{
|
|
int r;
|
|
struct tr_info *tr;
|
|
|
|
r = pcm_unregister(dev);
|
|
if (r)
|
|
return r;
|
|
|
|
tr = pcm_getdevinfo(dev);
|
|
bus_release_resource(dev, tr->regtype, tr->regid, tr->reg);
|
|
bus_teardown_intr(dev, tr->irq, tr->ih);
|
|
bus_release_resource(dev, SYS_RES_IRQ, tr->irqid, tr->irq);
|
|
bus_dma_tag_destroy(tr->parent_dmat);
|
|
snd_mtxfree(tr->lock);
|
|
free(tr, M_DEVBUF);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
tr_pci_suspend(device_t dev)
|
|
{
|
|
int i;
|
|
struct tr_info *tr;
|
|
|
|
tr = pcm_getdevinfo(dev);
|
|
|
|
for (i = 0; i < tr->playchns; i++) {
|
|
tr->chinfo[i].was_active = tr->chinfo[i].active;
|
|
if (tr->chinfo[i].active) {
|
|
trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_STOP);
|
|
}
|
|
}
|
|
|
|
tr->recchinfo.was_active = tr->recchinfo.active;
|
|
if (tr->recchinfo.active) {
|
|
trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_STOP);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
tr_pci_resume(device_t dev)
|
|
{
|
|
int i;
|
|
struct tr_info *tr;
|
|
|
|
tr = pcm_getdevinfo(dev);
|
|
|
|
if (tr_init(tr) == -1) {
|
|
device_printf(dev, "unable to initialize the card\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
if (mixer_reinit(dev) == -1) {
|
|
device_printf(dev, "unable to initialize the mixer\n");
|
|
return ENXIO;
|
|
}
|
|
|
|
for (i = 0; i < tr->playchns; i++) {
|
|
if (tr->chinfo[i].was_active) {
|
|
trpchan_trigger(NULL, &tr->chinfo[i], PCMTRIG_START);
|
|
}
|
|
}
|
|
|
|
if (tr->recchinfo.was_active) {
|
|
trrchan_trigger(NULL, &tr->recchinfo, PCMTRIG_START);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static device_method_t tr_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, tr_pci_probe),
|
|
DEVMETHOD(device_attach, tr_pci_attach),
|
|
DEVMETHOD(device_detach, tr_pci_detach),
|
|
DEVMETHOD(device_suspend, tr_pci_suspend),
|
|
DEVMETHOD(device_resume, tr_pci_resume),
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t tr_driver = {
|
|
"pcm",
|
|
tr_methods,
|
|
PCM_SOFTC_SIZE,
|
|
};
|
|
|
|
DRIVER_MODULE(snd_t4dwave, pci, tr_driver, pcm_devclass, 0, 0);
|
|
MODULE_DEPEND(snd_t4dwave, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
|
|
MODULE_VERSION(snd_t4dwave, 1);
|