369 lines
9.6 KiB
C
369 lines
9.6 KiB
C
/*-
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* Copyright 2004 by Peter Grehan. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Mac 'Kauai' PCI ATA controller
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*/
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/malloc.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <sys/ata.h>
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#include <dev/ata/ata-all.h>
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#include <ata_if.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <machine/intr_machdep.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include "ata_dbdma.h"
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#define ATA_KAUAI_REGOFFSET 0x2000
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#define ATA_KAUAI_DBDMAOFFSET 0x1000
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/*
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* Offset to alt-control register from base
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*/
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#define ATA_KAUAI_ALTOFFSET (ATA_KAUAI_REGOFFSET + 0x160)
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/*
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* Define the gap between registers
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*/
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#define ATA_KAUAI_REGGAP 16
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/*
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* PIO and DMA access registers
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*/
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#define PIO_CONFIG_REG (ATA_KAUAI_REGOFFSET + 0x200)
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#define UDMA_CONFIG_REG (ATA_KAUAI_REGOFFSET + 0x210)
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#define DMA_IRQ_REG (ATA_KAUAI_REGOFFSET + 0x300)
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#define USE_DBDMA_IRQ 0
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/*
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* Define the kauai pci bus attachment.
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*/
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static int ata_kauai_probe(device_t dev);
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static int ata_kauai_attach(device_t dev);
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static int ata_kauai_setmode(device_t dev, int target, int mode);
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static int ata_kauai_begin_transaction(struct ata_request *request);
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static device_method_t ata_kauai_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ata_kauai_probe),
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DEVMETHOD(device_attach, ata_kauai_attach),
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DEVMETHOD(device_detach, bus_generic_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* ATA interface */
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DEVMETHOD(ata_setmode, ata_kauai_setmode),
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{ 0, 0 }
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};
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struct ata_kauai_softc {
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struct ata_dbdma_channel sc_ch;
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struct resource *sc_memr;
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int shasta;
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uint32_t udmaconf[2];
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uint32_t wdmaconf[2];
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uint32_t pioconf[2];
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};
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static driver_t ata_kauai_driver = {
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"ata",
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ata_kauai_methods,
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sizeof(struct ata_kauai_softc),
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};
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DRIVER_MODULE(ata, pci, ata_kauai_driver, ata_devclass, 0, 0);
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MODULE_DEPEND(ata, ata, 1, 1, 1);
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/*
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* PCI ID search table
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*/
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static struct kauai_pci_dev {
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u_int32_t kpd_devid;
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char *kpd_desc;
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} kauai_pci_devlist[] = {
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{ 0x0033106b, "Uninorth2 Kauai ATA Controller" },
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{ 0x003b106b, "Intrepid Kauai ATA Controller" },
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{ 0x0043106b, "K2 Kauai ATA Controller" },
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{ 0x0050106b, "Shasta Kauai ATA Controller" },
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{ 0x0069106b, "Intrepid-2 Kauai ATA Controller" },
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{ 0, NULL }
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};
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/*
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* IDE transfer timings
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*/
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#define KAUAI_PIO_MASK 0xff000fff
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#define KAUAI_DMA_MASK 0x00fff000
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#define KAUAI_UDMA_MASK 0x0000ffff
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static const u_int pio_timing_kauai[] = {
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0x08000a92, /* PIO0 */
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0x0800060f, /* PIO1 */
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0x0800038b, /* PIO2 */
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0x05000249, /* PIO3 */
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0x04000148 /* PIO4 */
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};
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static const u_int pio_timing_shasta[] = {
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0x0a000c97, /* PIO0 */
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0x07000712, /* PIO1 */
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0x040003cd, /* PIO2 */
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0x0400028b, /* PIO3 */
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0x0400010a /* PIO4 */
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};
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static const u_int dma_timing_kauai[] = {
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0x00618000, /* WDMA0 */
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0x00209000, /* WDMA1 */
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0x00148000 /* WDMA2 */
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};
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static const u_int dma_timing_shasta[] = {
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0x00820800, /* WDMA0 */
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0x0028b000, /* WDMA1 */
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0x001ca000 /* WDMA2 */
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};
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static const u_int udma_timing_kauai[] = {
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0x000070c1, /* UDMA0 */
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0x00005d81, /* UDMA1 */
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0x00004a61, /* UDMA2 */
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0x00003a51, /* UDMA3 */
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0x00002a31, /* UDMA4 */
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0x00002921 /* UDMA5 */
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};
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static const u_int udma_timing_shasta[] = {
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0x00035901, /* UDMA0 */
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0x000348b1, /* UDMA1 */
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0x00033881, /* UDMA2 */
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0x00033861, /* UDMA3 */
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0x00033841, /* UDMA4 */
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0x00033031, /* UDMA5 */
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0x00033021 /* UDMA6 */
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};
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static int
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ata_kauai_probe(device_t dev)
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{
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struct ata_channel *ch;
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struct ata_kauai_softc *sc;
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u_int32_t devid;
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phandle_t node;
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const char *compatstring = NULL;
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int i, found, rid;
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found = 0;
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devid = pci_get_devid(dev);
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for (i = 0; kauai_pci_devlist[i].kpd_desc != NULL; i++) {
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if (devid == kauai_pci_devlist[i].kpd_devid) {
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found = 1;
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device_set_desc(dev, kauai_pci_devlist[i].kpd_desc);
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}
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}
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if (!found)
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return (ENXIO);
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node = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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bzero(sc, sizeof(struct ata_kauai_softc));
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ch = &sc->sc_ch.sc_ch;
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compatstring = ofw_bus_get_compat(dev);
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if (compatstring != NULL && strcmp(compatstring,"shasta-ata") == 0)
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sc->shasta = 1;
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/* Pre-K2 controllers apparently need this hack */
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if (!sc->shasta &&
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(compatstring == NULL || strcmp(compatstring, "K2-UATA") != 0))
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bus_set_resource(dev, SYS_RES_IRQ, 0, 39, 1);
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rid = PCIR_BARS;
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sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->sc_memr == NULL) {
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device_printf(dev, "could not allocate memory\n");
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return (ENXIO);
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}
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/*
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* Set up the resource vectors
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*/
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for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
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ch->r_io[i].res = sc->sc_memr;
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ch->r_io[i].offset = i*ATA_KAUAI_REGGAP + ATA_KAUAI_REGOFFSET;
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}
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ch->r_io[ATA_CONTROL].res = sc->sc_memr;
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ch->r_io[ATA_CONTROL].offset = ATA_KAUAI_ALTOFFSET;
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ata_default_registers(dev);
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ch->unit = 0;
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ch->flags |= ATA_USE_16BIT;
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ata_generic_hw(dev);
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return (ata_probe(dev));
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}
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#if USE_DBDMA_IRQ
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static int
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ata_kauai_dma_interrupt(struct ata_kauai_softc *sc)
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{
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/* Clear the DMA interrupt bits */
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bus_write_4(sc->sc_memr, DMA_IRQ_REG, 0x80000000);
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return ata_interrupt(sc);
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}
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#endif
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static int
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ata_kauai_attach(device_t dev)
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{
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struct ata_kauai_softc *sc = device_get_softc(dev);
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#if USE_DBDMA_IRQ
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int dbdma_irq_rid = 1;
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struct resource *dbdma_irq;
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void *cookie;
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#endif
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pci_enable_busmaster(dev);
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/* Init DMA engine */
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sc->sc_ch.dbdma_rid = 1;
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sc->sc_ch.dbdma_regs = sc->sc_memr;
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sc->sc_ch.dbdma_offset = ATA_KAUAI_DBDMAOFFSET;
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ata_dbdma_dmainit(dev);
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#if USE_DBDMA_IRQ
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/* Bind to DBDMA interrupt as well */
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if ((dbdma_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&dbdma_irq_rid, RF_SHAREABLE | RF_ACTIVE)) != NULL) {
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bus_setup_intr(dev, dbdma_irq, ATA_INTR_FLAGS, NULL,
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(driver_intr_t *)ata_kauai_dma_interrupt, sc,&cookie);
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}
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#endif
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/* Set up initial mode */
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sc->pioconf[0] = sc->pioconf[1] =
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bus_read_4(sc->sc_memr, PIO_CONFIG_REG) & 0x0f000fff;
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sc->udmaconf[0] = sc->udmaconf[1] = 0;
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sc->wdmaconf[0] = sc->wdmaconf[1] = 0;
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/* Magic FCR value from Apple */
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bus_write_4(sc->sc_memr, 0, 0x00000007);
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/* Set begin_transaction */
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sc->sc_ch.sc_ch.hw.begin_transaction = ata_kauai_begin_transaction;
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return ata_attach(dev);
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}
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static int
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ata_kauai_setmode(device_t dev, int target, int mode)
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{
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struct ata_kauai_softc *sc = device_get_softc(dev);
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mode = min(mode,sc->shasta ? ATA_UDMA6 : ATA_UDMA5);
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if (sc->shasta) {
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switch (mode & ATA_DMA_MASK) {
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case ATA_UDMA0:
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sc->udmaconf[target]
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= udma_timing_shasta[mode & ATA_MODE_MASK];
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break;
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case ATA_WDMA0:
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sc->udmaconf[target] = 0;
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sc->wdmaconf[target]
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= dma_timing_shasta[mode & ATA_MODE_MASK];
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break;
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default:
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sc->pioconf[target]
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= pio_timing_shasta[(mode & ATA_MODE_MASK) -
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ATA_PIO0];
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break;
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}
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} else {
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switch (mode & ATA_DMA_MASK) {
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case ATA_UDMA0:
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sc->udmaconf[target]
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= udma_timing_kauai[mode & ATA_MODE_MASK];
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break;
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case ATA_WDMA0:
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sc->udmaconf[target] = 0;
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sc->wdmaconf[target]
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= dma_timing_kauai[mode & ATA_MODE_MASK];
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break;
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default:
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sc->pioconf[target]
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= pio_timing_kauai[(mode & ATA_MODE_MASK)
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- ATA_PIO0];
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break;
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}
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}
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return (mode);
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}
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static int
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ata_kauai_begin_transaction(struct ata_request *request)
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{
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struct ata_kauai_softc *sc = device_get_softc(request->parent);
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bus_write_4(sc->sc_memr, UDMA_CONFIG_REG, sc->udmaconf[request->unit]);
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bus_write_4(sc->sc_memr, PIO_CONFIG_REG,
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sc->wdmaconf[request->unit] | sc->pioconf[request->unit]);
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return ata_begin_transaction(request);
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}
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