161 lines
5.1 KiB
C
161 lines
5.1 KiB
C
/*-
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* Copyright (c) 2005 Olivier Houchard. All rights reserved.
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* Copyright (c) 2010 Greg Ansley. All rights reserved.
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* Copyright (c) 2012 Andrew Turner. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91reg.h>
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#include <arm/at91/at91soc.h>
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#include <arm/at91/at91_aicreg.h>
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#include <arm/at91/at91sam9g45reg.h>
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#include <arm/at91/at91_pitreg.h>
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#include <arm/at91/at91_pmcreg.h>
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#include <arm/at91/at91_pmcvar.h>
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#include <arm/at91/at91_rstreg.h>
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/*
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* Standard priority levels for the system. 0 is lowest and 7 is highest.
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* These values are the ones Atmel uses for its Linux port
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*/
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static const int at91_irq_prio[32] =
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{
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7, /* Advanced Interrupt Controller */
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7, /* System Peripherals */
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1, /* Parallel IO Controller A */
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1, /* Parallel IO Controller B */
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1, /* Parallel IO Controller C */
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1, /* Parallel IO Controller D and E */
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0,
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5, /* USART 0 */
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5, /* USART 1 */
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5, /* USART 2 */
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5, /* USART 3 */
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0, /* Multimedia Card Interface 0 */
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6, /* Two-Wire Interface 0 */
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6, /* Two-Wire Interface 1 */
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5, /* Serial Peripheral Interface 0 */
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5, /* Serial Peripheral Interface 1 */
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4, /* Serial Synchronous Controller 0 */
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4, /* Serial Synchronous Controller 1 */
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0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
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0, /* Pulse Width Modulation Controller */
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0, /* Touch Screen Controller */
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0, /* DMA Controller */
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2, /* USB Host High Speed port */
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3, /* LCD Controller */
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5, /* AC97 Controller */
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3, /* Ethernet */
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0, /* Image Sensor Interface */
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2, /* USB Device High Speed port */
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0, /* (reserved) */
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0, /* Multimedia Card Interface 1 */
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0, /* (reserved) */
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0, /* Advanced Interrupt Controller IRQ0 */
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};
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#define DEVICE(_name, _id, _unit) \
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{ \
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_name, _unit, \
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AT91SAM9G45_ ## _id ##_BASE, \
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AT91SAM9G45_ ## _id ## _SIZE, \
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AT91SAM9G45_IRQ_ ## _id \
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}
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static const struct cpu_devs at91_devs[] =
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{
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DEVICE("at91_pmc", PMC, 0),
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DEVICE("at91_wdt", WDT, 0),
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DEVICE("at91_rst", RSTC, 0),
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DEVICE("at91_pit", PIT, 0),
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DEVICE("at91_pio", PIOA, 0),
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DEVICE("at91_pio", PIOB, 1),
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DEVICE("at91_pio", PIOC, 2),
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DEVICE("at91_pio", PIOD, 3),
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DEVICE("at91_pio", PIOE, 4),
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DEVICE("at91_twi", TWI0, 0),
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DEVICE("at91_twi", TWI1, 1),
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DEVICE("at91_mci", HSMCI0, 0),
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DEVICE("at91_mci", HSMCI1, 1),
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DEVICE("uart", DBGU, 0),
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DEVICE("uart", USART0, 1),
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DEVICE("uart", USART1, 2),
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DEVICE("uart", USART2, 3),
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DEVICE("uart", USART3, 4),
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DEVICE("spi", SPI0, 0),
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DEVICE("spi", SPI1, 1),
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DEVICE("ate", EMAC, 0),
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DEVICE("macb", EMAC, 0),
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DEVICE("nand", NAND, 0),
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DEVICE("ohci", OHCI, 0),
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{ 0, 0, 0, 0, 0 }
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};
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static void
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at91_clock_init(void)
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{
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struct at91_pmc_clock *clk;
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/* Update USB host port clock info */
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clk = at91_pmc_clock_ref("uhpck");
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clk->pmc_mask = PMC_SCER_UHP_SAM9;
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at91_pmc_clock_deref(clk);
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/* Each SOC has different PLL contraints */
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clk = at91_pmc_clock_ref("plla");
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clk->pll_min_in = SAM9G45_PLL_A_MIN_IN_FREQ; /* 2 MHz */
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clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */
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clk->pll_min_out = SAM9G45_PLL_A_MIN_OUT_FREQ; /* 400 MHz */
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clk->pll_max_out = SAM9G45_PLL_A_MAX_OUT_FREQ; /* 800 MHz */
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clk->pll_mul_shift = SAM9G45_PLL_A_MUL_SHIFT;
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clk->pll_mul_mask = SAM9G45_PLL_A_MUL_MASK;
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clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT;
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clk->pll_div_mask = SAM9G45_PLL_A_DIV_MASK;
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clk->set_outb = at91_pmc_800mhz_plla_outb;
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at91_pmc_clock_deref(clk);
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}
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static struct at91_soc_data soc_data = {
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.soc_delay = at91_pit_delay,
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.soc_reset = at91_rst_cpu_reset,
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.soc_clock_init = at91_clock_init,
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.soc_irq_prio = at91_irq_prio,
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.soc_children = at91_devs,
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};
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AT91_SOC(AT91_T_SAM9G45, &soc_data);
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