f57d04ab1d
register to the one of the processor doing the interrupt setup. This is required since this field is preinitialized to 0, but there exist machines which have no processor with a MID of 0 (e.g. e450s with 1 or 2 processors). Add some more macros for handle the interrupt mapping registers, and rename some existing ones for consistency. Approved by: re
75 lines
3.5 KiB
C
75 lines
3.5 KiB
C
/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* form: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
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* from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_BUS_COMMON_H_
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#define _MACHINE_BUS_COMMON_H_
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#define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */
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#define INTMAP_TID_MASK 0x07c000000LL /* UPA target ID */
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#define INTMAP_TID_SHIFT 26
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#define INTMAP_IGN_MASK 0x0000007c0LL /* Interrupt group no. */
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#define INTMAP_IGN_SHIFT 6
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#define INTMAP_INO_MASK 0x00000003fLL /* Interrupt number */
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#define INTMAP_INR_MASK (INTMAP_IGN_MASK | INTMAP_INO_MASK)
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#define INTMAP_SBUSSLOT_MASK 0x000000018LL /* SBUS slot # */
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#define INTMAP_PCIBUS_MASK 0x000000010LL /* PCI bus number (A or B) */
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#define INTMAP_PCISLOT_MASK 0x00000000cLL /* PCI slot # */
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#define INTMAP_PCIINT_MASK 0x000000003LL /* PCI interrupt #A,#B,#C,#D */
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#define INTMAP_OBIO_MASK 0x000000020LL /* Onboard device */
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#define INTVEC(x) ((x) & INTMAP_INR_MASK)
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#define INTSLOT(x) (((x) >> 3) & 0x7)
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#define INTPRI(x) ((x) & 0x7)
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#define INTINO(x) ((x) & INTMAP_INO_MASK)
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#define INTMAP_ENABLE(mr, mid) \
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(((mr) & ~INTMAP_TID_MASK) | ((mid) << INTMAP_TID_SHIFT) | INTMAP_V)
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/* counter-timer support. */
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void sparc64_counter_init(bus_space_tag_t tag, bus_space_handle_t handle,
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bus_addr_t offset);
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#endif /* !_MACHINE_BUS_COMMON_H_ */
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