517904de5c
This controller supports 2.5G/1G/100MB/10MB speeds, and allows
tx/rx checksum offload, TSO, LRO, and multi-queue operation.
The driver was derived from code contributed by Intel, and modified
by Netgate to fit into the iflib framework.
Thanks to Mike Karels for testing and feedback on the driver.
Reviewed by: bcr (manpages), kbowling, scottl, erj
MFC after: 1 month
Relnotes: yes
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D30668
431 lines
13 KiB
C
431 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
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* All rights reserved.
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* Copyright (c) 2021 Rubicon Communications, LLC (Netgate)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "opt_ddb.h"
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#include "opt_inet.h"
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#include "opt_inet6.h"
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#include "opt_rss.h"
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#ifdef HAVE_KERNEL_OPTION_HEADERS
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#include "opt_device_polling.h"
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#endif
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#include <sys/param.h>
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#include <sys/systm.h>
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#ifdef DDB
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#include <sys/types.h>
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#include <ddb/ddb.h>
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#endif
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#include <sys/buf_ring.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/smp.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <sys/eventhandler.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <net/bpf.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/iflib.h>
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#include <net/if_types.h>
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#include <net/if_vlan_var.h>
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#include <netinet/in_systm.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <netinet/ip.h>
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#include <netinet/ip6.h>
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#include <netinet/tcp.h>
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#include <netinet/udp.h>
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#include <machine/in_cksum.h>
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#include <dev/led/led.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include "igc_api.h"
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#include "igc_i225.h"
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#include "ifdi_if.h"
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#ifndef _IGC_H_DEFINED_
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#define _IGC_H_DEFINED_
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/* Tunables */
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/*
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* IGC_MAX_TXD: Maximum number of Transmit Descriptors
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* Valid Range: 128-4096
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* Default Value: 1024
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* This value is the number of transmit descriptors allocated by the driver.
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* Increasing this value allows the driver to queue more transmits. Each
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* descriptor is 16 bytes.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0
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*/
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#define IGC_MIN_TXD 128
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#define IGC_MAX_TXD 4096
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#define IGC_DEFAULT_TXD 1024
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#define IGC_DEFAULT_MULTI_TXD 4096
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#define IGC_MAX_TXD 4096
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/*
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* IGC_MAX_RXD - Maximum number of receive Descriptors
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* Valid Range: 128-4096
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* Default Value: 1024
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* This value is the number of receive descriptors allocated by the driver.
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* Increasing this value allows the driver to buffer more incoming packets.
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* Each descriptor is 16 bytes. A receive buffer is also allocated for each
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* descriptor. The maximum MTU size is 16110.
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* Since TDLEN should be multiple of 128bytes, the number of transmit
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* desscriptors should meet the following condition.
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* (num_tx_desc * sizeof(struct igc_tx_desc)) % 128 == 0
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*/
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#define IGC_MIN_RXD 128
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#define IGC_MAX_RXD 4096
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#define IGC_DEFAULT_RXD 1024
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#define IGC_DEFAULT_MULTI_RXD 4096
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#define IGC_MAX_RXD 4096
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/*
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* IGC_TIDV_VAL - Transmit Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value delays the generation of transmit interrupts in units of
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* 1.024 microseconds. Transmit interrupt reduction can improve CPU
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* efficiency if properly tuned for specific network traffic. If the
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* system is reporting dropped transmits, this value may be set too high
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* causing the driver to run out of available transmit descriptors.
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*/
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#define IGC_TIDV_VAL 64
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/*
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* IGC_TADV_VAL - Transmit Absolute Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* transmit interrupt is generated. Useful only if IGC_TIDV is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is sent on the wire within the set amount of time. Proper tuning,
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* along with IGC_TIDV_VAL, may improve traffic throughput in specific
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* network conditions.
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*/
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#define IGC_TADV_VAL 64
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/*
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* IGC_RDTR_VAL - Receive Interrupt Delay Timer (Packet Timer)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 0
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* This value delays the generation of receive interrupts in units of 1.024
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* microseconds. Receive interrupt reduction can improve CPU efficiency if
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* properly tuned for specific network traffic. Increasing this value adds
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* extra latency to frame reception and can end up decreasing the throughput
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* of TCP traffic. If the system is reporting dropped receives, this value
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* may be set too high, causing the driver to run out of available receive
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* descriptors.
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*
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* CAUTION: When setting IGC_RDTR to a value other than 0, adapters
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* may hang (stop transmitting) under certain network conditions.
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* If this occurs a WATCHDOG message is logged in the system
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* event log. In addition, the controller is automatically reset,
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* restoring the network connection. To eliminate the potential
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* for the hang ensure that IGC_RDTR is set to 0.
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*/
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#define IGC_RDTR_VAL 0
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/*
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* Receive Interrupt Absolute Delay Timer
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* receive interrupt is generated. Useful only if IGC_RDTR is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is received within the set amount of time. Proper tuning,
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* along with IGC_RDTR, may improve traffic throughput in specific network
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* conditions.
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*/
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#define IGC_RADV_VAL 64
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/*
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* This parameter controls whether or not autonegotation is enabled.
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* 0 - Disable autonegotiation
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* 1 - Enable autonegotiation
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*/
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#define DO_AUTO_NEG true
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/* Tunables -- End */
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#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
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ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
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ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)
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#define AUTO_ALL_MODES 0
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/*
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* Micellaneous constants
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*/
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#define MAX_NUM_MULTICAST_ADDRESSES 128
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#define IGC_FC_PAUSE_TIME 0x0680
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#define IGC_TXPBSIZE 20408
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#define IGC_PKTTYPE_MASK 0x0000FFF0
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#define IGC_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */
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#define IGC_RX_PTHRESH 8
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#define IGC_RX_HTHRESH 8
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#define IGC_RX_WTHRESH 4
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#define IGC_TX_PTHRESH 8
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#define IGC_TX_HTHRESH 1
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/*
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* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
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* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
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* also optimize cache line size effect. H/W supports up to cache line size 128.
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*/
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#define IGC_DBA_ALIGN 128
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#define IGC_MSIX_BAR 3
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/* Defines for printing debug information */
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#define DEBUG_INIT 0
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#define DEBUG_IOCTL 0
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#define DEBUG_HW 0
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#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n")
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#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A)
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#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B)
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#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n")
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#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A)
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#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B)
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#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n")
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#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A)
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#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B)
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#define IGC_MAX_SCATTER 40
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#define IGC_VFTA_SIZE 128
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#define IGC_TSO_SIZE 65535
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#define IGC_TSO_SEG_SIZE 4096 /* Max dma segment size */
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#define IGC_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \
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CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \
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CSUM_IP6_SCTP) /* Offload bits in mbuf flag */
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struct igc_adapter;
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struct igc_int_delay_info {
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struct igc_adapter *adapter; /* Back-pointer to the adapter struct */
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int offset; /* Register offset to read/write */
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int value; /* Current value in usecs */
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};
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/*
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* The transmit ring, one per tx queue
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*/
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struct tx_ring {
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struct igc_adapter *adapter;
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struct igc_tx_desc *tx_base;
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uint64_t tx_paddr;
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qidx_t *tx_rsq;
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uint8_t me;
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qidx_t tx_rs_cidx;
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qidx_t tx_rs_pidx;
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qidx_t tx_cidx_processed;
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/* Interrupt resources */
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void *tag;
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struct resource *res;
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unsigned long tx_irq;
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/* Saved csum offloading context information */
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int csum_flags;
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int csum_lhlen;
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int csum_iphlen;
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int csum_thlen;
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int csum_mss;
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int csum_pktlen;
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uint32_t csum_txd_upper;
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uint32_t csum_txd_lower; /* last field */
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};
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/*
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* The Receive ring, one per rx queue
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*/
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struct rx_ring {
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struct igc_adapter *adapter;
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struct igc_rx_queue *que;
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u32 me;
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u32 payload;
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union igc_rx_desc_extended *rx_base;
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uint64_t rx_paddr;
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/* Interrupt resources */
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void *tag;
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struct resource *res;
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/* Soft stats */
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unsigned long rx_irq;
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unsigned long rx_discarded;
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unsigned long rx_packets;
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unsigned long rx_bytes;
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};
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struct igc_tx_queue {
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struct igc_adapter *adapter;
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u32 msix;
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u32 eims; /* This queue's EIMS bit */
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u32 me;
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struct tx_ring txr;
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};
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struct igc_rx_queue {
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struct igc_adapter *adapter;
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u32 me;
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u32 msix;
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u32 eims;
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struct rx_ring rxr;
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u64 irqs;
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struct if_irq que_irq;
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};
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/* Our adapter structure */
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struct igc_adapter {
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struct ifnet *ifp;
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struct igc_hw hw;
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if_softc_ctx_t shared;
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if_ctx_t ctx;
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#define tx_num_queues shared->isc_ntxqsets
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#define rx_num_queues shared->isc_nrxqsets
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#define intr_type shared->isc_intr
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/* FreeBSD operating-system-specific structures. */
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struct igc_osdep osdep;
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device_t dev;
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struct cdev *led_dev;
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struct igc_tx_queue *tx_queues;
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struct igc_rx_queue *rx_queues;
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struct if_irq irq;
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struct resource *memory;
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struct resource *flash;
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struct resource *ioport;
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struct resource *res;
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void *tag;
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u32 linkvec;
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u32 ivars;
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struct ifmedia *media;
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int msix;
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int if_flags;
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int igc_insert_vlan_header;
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u32 ims;
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u32 flags;
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/* Task for FAST handling */
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struct grouptask link_task;
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u16 num_vlans;
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u32 txd_cmd;
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u32 tx_process_limit;
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u32 rx_process_limit;
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u32 rx_mbuf_sz;
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/* Management and WOL features */
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u32 wol;
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/* Multicast array memory */
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u8 *mta;
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/*
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** Shadow VFTA table, this is needed because
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** the real vlan filter table gets cleared during
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** a soft reset and the driver needs to be able
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** to repopulate it.
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*/
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u32 shadow_vfta[IGC_VFTA_SIZE];
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/* Info about the interface */
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u16 link_active;
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u16 fc;
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u16 link_speed;
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u16 link_duplex;
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u32 smartspeed;
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u32 dmac;
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int link_mask;
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u64 que_mask;
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struct igc_int_delay_info tx_int_delay;
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struct igc_int_delay_info tx_abs_int_delay;
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struct igc_int_delay_info rx_int_delay;
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struct igc_int_delay_info rx_abs_int_delay;
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struct igc_int_delay_info tx_itr;
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/* Misc stats maintained by the driver */
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unsigned long dropped_pkts;
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unsigned long link_irq;
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unsigned long rx_overruns;
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unsigned long watchdog_events;
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struct igc_hw_stats stats;
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u16 vf_ifp;
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};
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void igc_dump_rs(struct igc_adapter *);
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#define IGC_RSSRK_SIZE 4
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#define IGC_RSSRK_VAL(key, i) (key[(i) * IGC_RSSRK_SIZE] | \
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key[(i) * IGC_RSSRK_SIZE + 1] << 8 | \
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key[(i) * IGC_RSSRK_SIZE + 2] << 16 | \
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key[(i) * IGC_RSSRK_SIZE + 3] << 24)
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#endif /* _IGC_H_DEFINED_ */
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