561cd74b17
Summary:
The previously used software reset routine wasn't sufficient
to reset the PHY if the bootloader hadn't left the device in
an initialized state. This was seen with the onboard igc port
on an 11th-gen Intel NUC.
The software reset isn't used in the Linux driver so all related
code has been removed.
Tested on: Netgate 6100 onboard ports, a discrete PCIe I225-LM card,
and an 11th-gen Intel NUC.
Reported by: woodsb02
Tested by: woodsb02 (NUC)
MFC after: 3 days
Sponsored by: Rubicon Communications, LLC ("Netgate")
Reviewed by: kbowling
Differential Revision: https://reviews.freebsd.org/D32772
134 lines
5.4 KiB
C
134 lines
5.4 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* $FreeBSD$
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*/
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#ifndef _IGC_PHY_H_
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#define _IGC_PHY_H_
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void igc_init_phy_ops_generic(struct igc_hw *hw);
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s32 igc_null_read_reg(struct igc_hw *hw, u32 offset, u16 *data);
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void igc_null_phy_generic(struct igc_hw *hw);
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s32 igc_null_lplu_state(struct igc_hw *hw, bool active);
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s32 igc_null_write_reg(struct igc_hw *hw, u32 offset, u16 data);
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s32 igc_null_set_page(struct igc_hw *hw, u16 data);
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s32 igc_check_downshift_generic(struct igc_hw *hw);
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s32 igc_check_reset_block_generic(struct igc_hw *hw);
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s32 igc_get_phy_id(struct igc_hw *hw);
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void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl);
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s32 igc_phy_hw_reset_generic(struct igc_hw *hw);
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s32 igc_phy_reset_dsp_generic(struct igc_hw *hw);
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s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active);
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s32 igc_setup_copper_link_generic(struct igc_hw *hw);
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s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
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u32 usec_interval, bool *success);
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enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id);
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s32 igc_determine_phy_address(struct igc_hw *hw);
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s32 igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
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s32 igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
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void igc_power_up_phy_copper(struct igc_hw *hw);
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void igc_power_down_phy_copper(struct igc_hw *hw);
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s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data);
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s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data);
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s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
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u16 *data);
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s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
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u16 data);
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s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data);
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s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data);
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#define IGC_MAX_PHY_ADDR 8
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/* IGP01IGC Specific Registers */
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#define IGP01IGC_PHY_PORT_CONFIG 0x10 /* Port Config */
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#define IGP01IGC_PHY_PORT_STATUS 0x11 /* Status */
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#define IGP01IGC_PHY_PORT_CTRL 0x12 /* Control */
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#define IGP01IGC_PHY_LINK_HEALTH 0x13 /* PHY Link Health */
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#define IGP02IGC_PHY_POWER_MGMT 0x19 /* Power Management */
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#define IGP01IGC_PHY_PAGE_SELECT 0x1F /* Page Select */
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#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
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#define IGP_PAGE_SHIFT 5
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#define PHY_REG_MASK 0x1F
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#define IGC_I225_PHPM 0x0E14 /* I225 PHY Power Management */
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#define IGC_I225_PHPM_DIS_1000_D3 0x0008 /* Disable 1G in D3 */
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#define IGC_I225_PHPM_LINK_ENERGY 0x0010 /* Link Energy Detect */
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#define IGC_I225_PHPM_GO_LINKD 0x0020 /* Go Link Disconnect */
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#define IGC_I225_PHPM_DIS_1000 0x0040 /* Disable 1G globally */
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#define IGC_I225_PHPM_SPD_B2B_EN 0x0080 /* Smart Power Down Back2Back */
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#define IGC_I225_PHPM_RST_COMPL 0x0100 /* PHY Reset Completed */
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#define IGC_I225_PHPM_DIS_100_D3 0x0200 /* Disable 100M in D3 */
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#define IGC_I225_PHPM_ULP 0x0400 /* Ultra Low-Power Mode */
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#define IGC_I225_PHPM_DIS_2500 0x0800 /* Disable 2.5G globally */
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#define IGC_I225_PHPM_DIS_2500_D3 0x1000 /* Disable 2.5G in D3 */
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/* GPY211 - I225 defines */
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#define GPY_MMD_MASK 0xFFFF0000
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#define GPY_MMD_SHIFT 16
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#define GPY_REG_MASK 0x0000FFFF
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#define IGP01IGC_PHY_PCS_INIT_REG 0x00B4
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#define IGP01IGC_PHY_POLARITY_MASK 0x0078
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#define IGP01IGC_PSCR_AUTO_MDIX 0x1000
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#define IGP01IGC_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
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#define IGP01IGC_PSCFR_SMART_SPEED 0x0080
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#define IGP02IGC_PM_SPD 0x0001 /* Smart Power Down */
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#define IGP02IGC_PM_D0_LPLU 0x0002 /* For D0a states */
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#define IGP02IGC_PM_D3_LPLU 0x0004 /* For all other states */
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#define IGP01IGC_PLHR_SS_DOWNGRADE 0x8000
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#define IGP01IGC_PSSR_POLARITY_REVERSED 0x0002
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#define IGP01IGC_PSSR_MDIX 0x0800
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#define IGP01IGC_PSSR_SPEED_MASK 0xC000
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#define IGP01IGC_PSSR_SPEED_1000MBPS 0xC000
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#define IGP02IGC_PHY_CHANNEL_NUM 4
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#define IGP02IGC_PHY_AGC_A 0x11B1
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#define IGP02IGC_PHY_AGC_B 0x12B1
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#define IGP02IGC_PHY_AGC_C 0x14B1
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#define IGP02IGC_PHY_AGC_D 0x18B1
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#define IGP02IGC_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */
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#define IGP02IGC_AGC_LENGTH_MASK 0x7F
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#define IGP02IGC_AGC_RANGE 15
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#define IGC_CABLE_LENGTH_UNDEFINED 0xFF
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#define IGC_KMRNCTRLSTA_OFFSET 0x001F0000
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#define IGC_KMRNCTRLSTA_OFFSET_SHIFT 16
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#define IGC_KMRNCTRLSTA_REN 0x00200000
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#define IGC_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */
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#define IGC_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */
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#define IGC_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */
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#define IGC_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
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#define IGC_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */
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#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
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#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
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#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */
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#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
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/* IFE PHY Extended Status Control */
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#define IFE_PESC_POLARITY_REVERSED 0x0100
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/* IFE PHY Special Control */
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#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010
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#define IFE_PSC_FORCE_POLARITY 0x0020
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/* IFE PHY Special Control and LED Control */
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#define IFE_PSCL_PROBE_MODE 0x0020
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#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
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#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
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/* IFE PHY MDIX Control */
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#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
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#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
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#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */
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#endif
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