154 lines
5.3 KiB
C
154 lines
5.3 KiB
C
/*-
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* Copyright (c) 2008 Nathan Whitehorn
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_DBDMA_H_
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#define _MACHINE_DBDMA_H_
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#include <sys/param.h>
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#include <machine/bus.h>
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/*
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* Apple's DBDMA (Descriptor-based DMA) interface is a common DMA engine
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* used by a variety of custom Apple ASICs. It is described in the CHRP
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* specification and in the book Macintosh Technology in the Common
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* Hardware Reference Platform, copyright 1995 Apple Computer.
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*/
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/* DBDMA Command Values */
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enum {
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DBDMA_OUTPUT_MORE = 0,
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DBDMA_OUTPUT_LAST = 1,
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DBDMA_INPUT_MORE = 2,
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DBDMA_INPUT_LAST = 3,
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DBDMA_STORE_QUAD = 4,
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DBDMA_LOAD_QUAD = 5,
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DBDMA_NOP = 6,
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DBDMA_STOP = 7
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};
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/* These codes are for the interrupt, branch, and wait flags */
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enum {
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DBDMA_NEVER = 0,
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DBDMA_COND_TRUE = 1,
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DBDMA_COND_FALSE = 2,
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DBDMA_ALWAYS = 3
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};
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/* Channel status bits */
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#define DBDMA_STATUS_RUN (0x01 << 15)
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#define DBDMA_STATUS_PAUSE (0x01 << 14)
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#define DBDMA_STATUS_FLUSH (0x01 << 13)
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#define DBDMA_STATUS_WAKE (0x01 << 12)
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#define DBDMA_STATUS_DEAD (0x01 << 11)
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#define DBDMA_STATUS_ACTIVE (0x01 << 10)
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/* Set by hardware if a branch was taken */
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#define DBDMA_STATUS_BRANCH 8
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struct dbdma_command;
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typedef struct dbdma_command dbdma_command_t;
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struct dbdma_channel;
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typedef struct dbdma_channel dbdma_channel_t;
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int dbdma_allocate_channel(struct resource *dbdma_regs, u_int offset,
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bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan);
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int dbdma_resize_channel(dbdma_channel_t *chan, int newslots);
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int dbdma_free_channel(dbdma_channel_t *chan);
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void dbdma_run(dbdma_channel_t *chan);
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void dbdma_stop(dbdma_channel_t *chan);
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void dbdma_reset(dbdma_channel_t *chan);
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void dbdma_set_current_cmd(dbdma_channel_t *chan, int slot);
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void dbdma_pause(dbdma_channel_t *chan);
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void dbdma_wake(dbdma_channel_t *chan);
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/*
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* DBDMA uses a 16 bit channel control register to describe the current
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* state of DMA on the channel. The high-order bits (8-15) contain information
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* on the run state and are listed in the DBDMA_STATUS_* constants above. These
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* are manipulated with the dbdma_run/stop/reset() routines above.
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*
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* The low order bits (0-7) are device dependent status bits. These can be set
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* and read by both hardware and software. The mask is the set of bits to
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* modify; if mask is 0x03 and value is 0, the lowest order 2 bits will be
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* zeroed.
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*/
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uint16_t dbdma_get_chan_status(dbdma_channel_t *chan);
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uint8_t dbdma_get_device_status(dbdma_channel_t *chan);
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void dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask,
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uint8_t value);
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/*
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* Each DBDMA command word has the current channel status register and the
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* number of residual bytes (requested - actually transferred) written to it
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* at time of command completion.
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*/
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uint16_t dbdma_get_cmd_status(dbdma_channel_t *chan, int slot);
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uint16_t dbdma_get_residuals(dbdma_channel_t *chan, int slot);
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void dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot);
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/*
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* The interrupt/branch/wait selector let you specify a set of values
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* of the device dependent status bits that will cause intterupt/branch/wait
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* conditions to be taken if the flags for these are set to one of the
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* DBDMA_COND_* values.
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*
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* The condition is considered true if (status & mask) == value.
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*/
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void dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask,
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uint8_t value);
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void dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask,
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uint8_t value);
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void dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask,
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uint8_t value);
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void dbdma_insert_command(dbdma_channel_t *chan, int slot, int command,
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int stream, bus_addr_t data, size_t count, uint8_t interrupt,
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uint8_t branch, uint8_t wait, uint32_t branch_slot);
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void dbdma_insert_stop(dbdma_channel_t *chan, int slot);
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void dbdma_insert_nop(dbdma_channel_t *chan, int slot);
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void dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot);
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void dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op);
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void dbdma_save_state(dbdma_channel_t *chan);
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void dbdma_restore_state(dbdma_channel_t *chan);
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#endif /* _MACHINE_DBDMA_H_ */
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