498b9fa710
This function works with all smp non-multicluster allwinner SoC (A20, A31, A31S and H3). Approved by: cognet (mentor) Differential Revision: https://reviews.freebsd.org/D6269
287 lines
8.7 KiB
C
287 lines
8.7 KiB
C
/*-
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* Copyright (c) 2014 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* Copyright (c) 2016 Emmanuel Vadot <manu@bidouilliste.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/cpu-v6.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#include <machine/platformvar.h>
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#include <arm/allwinner/aw_mp.h>
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#include <arm/allwinner/allwinner_machdep.h>
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/* Register for all dual-core SoC */
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#define A20_CPUCFG_BASE 0x01c25c00
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/* Register for all quad-core SoC */
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#define CPUCFG_BASE 0x01f01c00
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#define CPUCFG_SIZE 0x400
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#define PRCM_BASE 0x01f01400
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#define PRCM_SIZE 0x800
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/* Register for multi-cluster SoC */
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#define CPUXCFG_BASE 0x01700000
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#define CPUXCFG_SIZE 0x400
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#define CPU_OFFSET 0x40
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#define CPU_OFFSET_CTL 0x04
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#define CPU_OFFSET_STATUS 0x08
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#define CPU_RST_CTL(cpuid) ((cpuid + 1) * CPU_OFFSET)
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#define CPU_CTL(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_CTL)
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#define CPU_STATUS(cpuid) (((cpuid + 1) * CPU_OFFSET) + CPU_OFFSET_STATUS)
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#define CPU_RESET (1 << 0)
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#define CPU_CORE_RESET (1 << 1)
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#define CPUCFG_GENCTL 0x184
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#define CPUCFG_P_REG0 0x1a4
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#define A20_CPU1_PWR_CLAMP 0x1b0
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#define CPU_PWR_CLAMP_REG 0x140
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#define CPU_PWR_CLAMP(cpu) ((cpu * 4) + CPU_PWR_CLAMP_REG)
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#define CPU_PWR_CLAMP_STEPS 8
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#define A20_CPU1_PWROFF_REG 0x1b4
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#define CPU_PWROFF 0x100
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#define CPUCFG_DBGCTL0 0x1e0
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#define CPUCFG_DBGCTL1 0x1e4
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#define CPUS_CL_RST(cl) (0x30 + (cluster) * 0x4)
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#define CPUX_CL_CTRL0(cl) (0x0 + (cluster) * 0x10)
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#define CPUX_CL_CTRL1(cl) (0x4 + (cluster) * 0x10)
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#define CPUX_CL_CPU_STATUS(cl) (0x30 + (cluster) * 0x4)
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#define CPUX_CL_RST(cl) (0x80 + (cluster) * 0x4)
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#define PRCM_CL_PWROFF(cl) (0x100 + (cluster) * 0x4)
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#define PRCM_CL_PWR_CLAMP(cl, cpu) (0x140 + (cluster) * 0x4 + (cpu) * 0x4)
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void
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aw_mp_setmaxid(platform_t plat)
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{
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int ncpu;
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uint32_t reg;
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if (mp_ncpus != 0)
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return;
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reg = cp15_l2ctlr_get();
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ncpu = CPUV7_L2CTLR_NPROC(reg);
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mp_ncpus = ncpu;
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mp_maxid = ncpu - 1;
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}
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void
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aw_mp_start_ap(platform_t plat)
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{
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bus_space_handle_t cpucfg;
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bus_space_handle_t prcm;
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int i, j, soc_family;
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uint32_t val;
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soc_family = allwinner_soc_family();
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if (soc_family == ALLWINNERSOC_SUN7I) {
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if (bus_space_map(fdtbus_bs_tag, A20_CPUCFG_BASE, CPUCFG_SIZE,
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0, &cpucfg) != 0)
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panic("Couldn't map the CPUCFG\n");
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} else {
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if (bus_space_map(fdtbus_bs_tag, CPUCFG_BASE, CPUCFG_SIZE,
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0, &cpucfg) != 0)
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panic("Couldn't map the CPUCFG\n");
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if (bus_space_map(fdtbus_bs_tag, PRCM_BASE, PRCM_SIZE, 0,
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&prcm) != 0)
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panic("Couldn't map the PRCM\n");
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}
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dcache_wbinv_poc_all();
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_P_REG0,
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pmap_kextract((vm_offset_t)mpentry));
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/*
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* Assert nCOREPORESET low and set L1RSTDISABLE low.
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* Ensure DBGPWRDUP is set to LOW to prevent any external
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* debug access to the processor.
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*/
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for (i = 1; i < mp_ncpus; i++)
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU_RST_CTL(i), 0);
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/* Set L1RSTDISABLE low */
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val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL);
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for (i = 1; i < mp_ncpus; i++)
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val &= ~(1 << i);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_GENCTL, val);
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/* Set DBGPWRDUP low */
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val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1);
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for (i = 1; i < mp_ncpus; i++)
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val &= ~(1 << i);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val);
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/* Release power clamp */
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for (i = 1; i < mp_ncpus; i++)
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for (j = 0; j <= CPU_PWR_CLAMP_STEPS; j++) {
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if (soc_family != ALLWINNERSOC_SUN7I) {
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bus_space_write_4(fdtbus_bs_tag, prcm,
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CPU_PWR_CLAMP(i), 0xff >> j);
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} else {
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bus_space_write_4(fdtbus_bs_tag,
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cpucfg, A20_CPU1_PWR_CLAMP, 0xff >> j);
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}
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}
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DELAY(10000);
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/* Clear power-off gating */
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if (soc_family != ALLWINNERSOC_SUN7I) {
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val = bus_space_read_4(fdtbus_bs_tag, prcm, CPU_PWROFF);
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for (i = 0; i < mp_ncpus; i++)
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val &= ~(1 << i);
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bus_space_write_4(fdtbus_bs_tag, prcm, CPU_PWROFF, val);
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} else {
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val = bus_space_read_4(fdtbus_bs_tag,
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cpucfg, A20_CPU1_PWROFF_REG);
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val &= ~(1 << 0);
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bus_space_write_4(fdtbus_bs_tag, cpucfg,
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A20_CPU1_PWROFF_REG, val);
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}
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DELAY(1000);
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/* De-assert cpu core reset */
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for (i = 1; i < mp_ncpus; i++)
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPU_RST_CTL(i),
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CPU_RESET | CPU_CORE_RESET);
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/* Assert DBGPWRDUP signal */
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val = bus_space_read_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1);
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for (i = 1; i < mp_ncpus; i++)
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val |= (1 << i);
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bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_DBGCTL1, val);
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armv7_sev();
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bus_space_unmap(fdtbus_bs_tag, cpucfg, CPUCFG_SIZE);
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if (soc_family != ALLWINNERSOC_SUN7I)
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bus_space_unmap(fdtbus_bs_tag, prcm, PRCM_SIZE);
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}
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static void
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aw_mc_mp_start_cpu(bus_space_handle_t cpuscfg, bus_space_handle_t cpuxcfg,
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bus_space_handle_t prcm, int cluster, int cpu)
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{
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uint32_t val;
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int i;
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/* Assert core reset */
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val = bus_space_read_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_RST(cluster));
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val &= ~(1 << cpu);
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bus_space_write_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_RST(cluster), val);
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/* Assert power-on reset */
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val = bus_space_read_4(fdtbus_bs_tag, cpuscfg, CPUS_CL_RST(cluster));
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val &= ~(1 << cpu);
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bus_space_write_4(fdtbus_bs_tag, cpuscfg, CPUS_CL_RST(cluster), val);
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/* Disable automatic L1 cache invalidate at reset */
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val = bus_space_read_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_CTRL0(cluster));
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val &= ~(1 << cpu);
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bus_space_write_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_CTRL0(cluster), val);
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/* Release power clamp */
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for (i = 0; i <= CPU_PWR_CLAMP_STEPS; i++)
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bus_space_write_4(fdtbus_bs_tag, prcm,
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PRCM_CL_PWR_CLAMP(cluster, cpu), 0xff >> i);
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while (bus_space_read_4(fdtbus_bs_tag, prcm,
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PRCM_CL_PWR_CLAMP(cluster, cpu)) != 0)
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;
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/* Clear power-off gating */
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val = bus_space_read_4(fdtbus_bs_tag, prcm, PRCM_CL_PWROFF(cluster));
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val &= ~(1 << cpu);
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bus_space_write_4(fdtbus_bs_tag, prcm, PRCM_CL_PWROFF(cluster), val);
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/* De-assert power-on reset */
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val = bus_space_read_4(fdtbus_bs_tag, cpuscfg, CPUS_CL_RST(cluster));
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val |= (1 << cpu);
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bus_space_write_4(fdtbus_bs_tag, cpuscfg, CPUS_CL_RST(cluster), val);
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/* De-assert core reset */
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val = bus_space_read_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_RST(cluster));
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val |= (1 << cpu);
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bus_space_write_4(fdtbus_bs_tag, cpuxcfg, CPUX_CL_RST(cluster), val);
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}
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static void
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aw_mc_mp_start_ap(bus_space_handle_t cpuscfg, bus_space_handle_t cpuxcfg,
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bus_space_handle_t prcm)
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{
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int cluster, cpu;
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KASSERT(mp_ncpus <= 4, ("multiple clusters not yet supported"));
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dcache_wbinv_poc_all();
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bus_space_write_4(fdtbus_bs_tag, cpuscfg, CPUCFG_P_REG0,
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pmap_kextract((vm_offset_t)mpentry));
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cluster = 0;
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for (cpu = 1; cpu < mp_ncpus; cpu++)
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aw_mc_mp_start_cpu(cpuscfg, cpuxcfg, prcm, cluster, cpu);
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}
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void
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a83t_mp_start_ap(platform_t plat)
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{
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bus_space_handle_t cpuscfg, cpuxcfg, prcm;
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if (bus_space_map(fdtbus_bs_tag, CPUCFG_BASE, CPUCFG_SIZE,
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0, &cpuscfg) != 0)
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panic("Couldn't map the CPUCFG\n");
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if (bus_space_map(fdtbus_bs_tag, CPUXCFG_BASE, CPUXCFG_SIZE,
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0, &cpuxcfg) != 0)
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panic("Couldn't map the CPUXCFG\n");
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if (bus_space_map(fdtbus_bs_tag, PRCM_BASE, PRCM_SIZE, 0,
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&prcm) != 0)
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panic("Couldn't map the PRCM\n");
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aw_mc_mp_start_ap(cpuscfg, cpuxcfg, prcm);
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armv7_sev();
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bus_space_unmap(fdtbus_bs_tag, cpuxcfg, CPUXCFG_SIZE);
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bus_space_unmap(fdtbus_bs_tag, cpuscfg, CPUCFG_SIZE);
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bus_space_unmap(fdtbus_bs_tag, prcm, PRCM_SIZE);
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}
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