1d556f272c
* Force the arge0 interface to not use a PHY for speed negotiation for now. It'd be nice to do it, but right now the RGMII interface to the switch needs to stay at 1000/full in order to match what the switch side of the port is programmed as. So until that's all sorted out, disconnect arge0 from the PHY and leave it at fixed at 1000/full. I noticed this when I tried using a busted ethernet cable that forced the PHY to negotiate 100/full. The switch was fine and it negotiated to 100/full, but then arge0 saw the link update and set the speed to 100/full when the switch side of that hook up was set to 1000/full. Tsk. * When using argemdio, the mdio device resets and initialises the MAC, /not/ the arge_attach (or, as I discovered, arge_init.) So arge1 wasn't being fully initialised and thus no traffic would ever flow. So until I tidy up that mess, just create an argemdio bus for arge1. It's totally fine; it won't do anything or find anything attached to it. Tested: * AP135 reference board - both arge0 and arge1 now work.
175 lines
4.8 KiB
Plaintext
175 lines
4.8 KiB
Plaintext
# This is a placeholder until the hardware support is complete.
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# I'm assuming this is an AP135-020. The AP136-010 in openwrt has
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# the ethernet ports wired up to the switch in the reverse way.
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# $FreeBSD$
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# QCA955X_ETH_CFG_RGMII_EN (1 << 0)
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hint.qca955x_gmac.0.gmac_cfg=0x1
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# mdiobus0 on arge0
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hint.argemdio.0.at="nexus0"
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hint.argemdio.0.maddr=0x19000000
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hint.argemdio.0.msize=0x1000
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hint.argemdio.0.order=0
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# mdiobus1 on arge1 - required to bring up arge1?
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hint.argemdio.1.at="nexus0"
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hint.argemdio.1.maddr=0x1a000000
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hint.argemdio.1.msize=0x1000
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hint.argemdio.1.order=0
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# AR8327 - connected via mdiobus0 on arge0
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hint.arswitch.0.at="mdio0"
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hint.arswitch.0.is_7240=0 # definitely not the internal switch!
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hint.arswitch.0.is_9340=0 # not the internal switch!
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hint.arswitch.0.numphys=5 # all ports are PHYs
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hint.arswitch.0.phy4cpu=0
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hint.arswitch.0.is_rgmii=0 # not needed
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hint.arswitch.0.is_gmii=0 # not needed
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# This is where it gets a bit odd. port 0 and port 6 are CPU ports.
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# The current code only supports one CPU port. So hm, what should
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# we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
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# The other trick - how do we get arge1 (hooked up to GMAC0) to work?
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# That's currently supposed to be hooked up to CPU port 0.
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# Other AR8327 configuration parameters
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# AP136-020 parameters
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# GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
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# AR8327_PAD_MAC_SGMII
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hint.arswitch.0.pad.0.mode=3
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#hint.arswitch.0.pad.0.rxclk_delay_sel=0
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hint.arswitch.0.pad.0.sgmii_delay_en=1
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# GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
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# AR8327_PAD_MAC_RGMII
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# XXX I think this hooks it up to the internal MAC6
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hint.arswitch.0.pad.6.mode=6
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hint.arswitch.0.pad.6.txclk_delay_en=1
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hint.arswitch.0.pad.6.rxclk_delay_en=1
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# AR8327_CLK_DELAY_SEL1
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hint.arswitch.0.pad.6.txclk_delay_sel=1
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# AR8327_CLK_DELAY_SEL2
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hint.arswitch.0.pad.6.rxclk_delay_sel=2
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# XXX there's no LED management just yet!
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hint.arswitch.0.led.ctrl0=0x00000000
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hint.arswitch.0.led.ctrl1=0xc737c737
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hint.arswitch.0.led.ctrl2=0x00000000
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hint.arswitch.0.led.ctrl3=0x00c30c00
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hint.arswitch.0.led.open_drain=1
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# force_link=1 is required for the rest of the parameters
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# to be configured.
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hint.arswitch.0.port.0.force_link=1
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hint.arswitch.0.port.0.speed=1000
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hint.arswitch.0.port.0.duplex=1
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hint.arswitch.0.port.0.txpause=1
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hint.arswitch.0.port.0.rxpause=1
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# force_link=1 is required for the rest of the parameters
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# to be configured.
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hint.arswitch.0.port.6.force_link=1
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hint.arswitch.0.port.6.speed=1000
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hint.arswitch.0.port.6.duplex=1
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hint.arswitch.0.port.6.txpause=1
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hint.arswitch.0.port.6.rxpause=1
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# arge0 - hooked up to AR8327 GMAC6, RGMII
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hint.arge.0.phymask=0x0
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hint.arge.0.miimode=3 # RGMII
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hint.arge.0.media=1000
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hint.arge.0.fduplex=1
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hint.arge.0.pll_1000=0x56000000
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# MAC for arge0 is the first 6 bytes of the ART
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hint.arge.0.eeprommac=0x1fff0000
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# arge1 - lock up to 1000/full
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hint.arge.1.phymask=0x0
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hint.arge.1.media=1000
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hint.arge.1.fduplex=1
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hint.arge.1.miimode=5 # SGMII
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hint.arge.1.pll_1000=0x03000101
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# MAC for arge1 is the second 6 bytes of the ART
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hint.arge.1.eeprommac=0x1fff0006
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# ath0: Where the ART is - last 64k in the flash
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hint.ath.0.eepromaddr=0x1fff0000
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hint.ath.0.eepromsize=16384
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# ath1: it's different; it's a PCIe attached device, so
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# we instead need to teach the PCIe bridge code about it
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# (ie, the 'early pci fixup' stuff that programs the PCIe
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# host registers on the NIC) and then we teach ath where
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# to find it.
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# ath1 hint - pcie slot 0
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hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
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hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
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# ath0 - eeprom comes from here
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hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
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# flash layout:
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#
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# bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),8256k(mib0),64k(ART)
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# 256KiB u-boot
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hint.map.0.at="flash/spi0"
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hint.map.0.start=0x00000000
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hint.map.0.end=0x00040000 # 256k u-boot
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hint.map.0.name="u-boot"
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hint.map.0.readonly=1
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# 64KiB u-boot-env
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hint.map.1.at="flash/spi0"
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hint.map.1.start=0x00040000
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hint.map.1.end=0x00050000 # 64k u-boot-env
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hint.map.1.name="u-boot-env"
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hint.map.1.readonly=1
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# 6336KiB rootfs
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hint.map.2.at="flash/spi0"
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hint.map.2.start=0x00050000
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hint.map.2.end=0x00680000 # 6336k rootfs
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hint.map.2.name="rootfs"
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hint.map.2.readonly=1
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# 1344KiB uImage
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hint.map.3.at="flash/spi0"
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hint.map.3.start=0x00680000
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hint.map.3.end=0x007d0000 # 1408k uImage, 64k off the end..
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hint.map.3.name="uImage"
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hint.map.3.readonly=1
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# 64KiB cfg
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hint.map.4.at="flash/spi0"
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hint.map.4.start=0x007d0000
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hint.map.4.end=0x007e0000
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hint.map.4.name="cfg"
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hint.map.4.readonly=0
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# 8256 KiB mib0
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hint.map.5.at="flash/spi0"
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hint.map.5.start=0x007e0000
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hint.map.5.end=0x00ff0000 # 64k mib0
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hint.map.5.name="mib0"
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hint.map.5.readonly=1
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# 64KiB ART
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hint.map.6.at="flash/spi0"
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hint.map.6.start=0x007f0000
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hint.map.6.end=0x01000000 # 64k ART
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hint.map.6.name="ART"
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hint.map.6.readonly=1
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