fb76025135
This is enough to bring up the basic SoC support. What works thus far: * The mips74k core, pll setup, and UART (or else well, stuff would be really difficult..) * both USB 2.0 EHCI controllers * on-board 2GHz 3x3 wifi (the other variant has 2GHz/5GHz wifi on-chip); * arge0 - not yet sure why arge1 isn't firing off interrupts and thus handling traffic, but I will soon figure it out and fix it here. Tested: * AP135 reference design, QCA9558 SoC, pretending to be an 11n 2GHz AP. TODO: * There's an interrupt mux hooking up devices to IP2 and IP3 - but it's not a read-and-clear or write-to-clear register. So, trying to use it naively like I have been ends up with massive interrupt storms. For now the things that share those interrupts can just take them as shared interrupts and try to play nice. * There's two PCIe root complexes /and/ one of them can actually be a PCIe device endpoint. Yes, you heard right. I have to teach the AR724x PCIe bridge code to handle multiple instances with multiple memory/irq regions, and then there'll be RC support, but EP support isn't on my TODO list. * I'm not sure why arge1 isn't up and running. I'll go figure that out soon and fix it here. Thankyou to Qualcomm Atheros for providing me with hardware and an abundance of documentation about these things.
80 lines
1.8 KiB
Plaintext
80 lines
1.8 KiB
Plaintext
# This file (and the kernel config file accompanying it) are not designed
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# to be used by themselves. Instead, users of this file should create a
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# kernel config file which includes this file (which gets the basic hints),
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# then override the default options (adding devices as needed) and adding
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# hints as needed (for example, the GPIO and LAN PHY.)
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# $FreeBSD$
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hint.apb.0.at="nexus0"
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# The default APB is on IP6 (irq4); we need to add
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# the two new ones (IP2, IP3) to this and extend
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# the irq ranges appropriately.
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hint.apb.0.irq=4
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# uart0
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hint.uart.0.at="apb0"
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# NB: This isn't an ns8250 UART
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hint.uart.0.maddr=0x18020003
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hint.uart.0.msize=0x18
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hint.uart.0.irq=3
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# ehci - on IP3
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hint.ehci.0.at="nexus0"
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hint.ehci.0.maddr=0x1b000100
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hint.ehci.0.msize=0x00001000
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hint.ehci.0.irq=1
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hint.ehci.1.at="nexus0"
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hint.ehci.1.maddr=0x1b400100
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hint.ehci.1.msize=0x00001000
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hint.ehci.1.irq=1
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# PCIe 1: qca955x_int0 (IP2)
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# pci - XXX no maddr/msize, grr!
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hint.pcib.0.at="nexus0"
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hint.pcib.0.irq=0
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# XXX TODO: PCIe 1: qca955x_int1 (IP3)
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# IP4
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hint.arge.0.at="nexus0"
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hint.arge.0.maddr=0x19000000
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hint.arge.0.msize=0x1000
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hint.arge.0.irq=2
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# IP5
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hint.arge.1.at="nexus0"
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hint.arge.1.maddr=0x1a000000
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hint.arge.1.msize=0x1000
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hint.arge.1.irq=3
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# ath0 - connected via IP2 mux
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hint.ath.0.at="nexus0"
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hint.ath.0.maddr=0x18100000
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hint.ath.0.msize=0x20000
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hint.ath.0.irq=0
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hint.ath.0.vendor_id=0x168c
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hint.ath.0.device_id=0x0039
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# Set this to define where the ath calibration data
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# should be fetched from in physical memory.
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# hint.ath.0.eepromaddr=0x1fff1000
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# SPI flash
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hint.spi.0.at="nexus0"
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hint.spi.0.maddr=0x1f000000
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hint.spi.0.msize=0x10
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hint.mx25l.0.at="spibus0"
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hint.mx25l.0.cs=0
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# Watchdog
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hint.ar71xx_wdog.0.at="nexus0"
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# The GPIO function and pin mask is configured per-board
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hint.gpio.0.at="apb0"
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hint.gpio.0.maddr=0x18040000
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hint.gpio.0.msize=0x1000
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hint.gpio.0.irq=2
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