121 lines
5.2 KiB
C
121 lines
5.2 KiB
C
/*-
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* Copyright (c) 2005 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91_PMCREG_H
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#define ARM_AT91_AT91_PMCREG_H
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/* Registers */
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#define PMC_SCER 0x00 /* System Clock Enable Register */
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#define PMC_SCDR 0x04 /* System Clock Disable Register */
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#define PMC_SCSR 0x08 /* System Clock Status Register */
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/* 0x0c reserved */
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#define PMC_PCER 0x10 /* Peripheral Clock Enable Register */
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#define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */
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#define PMC_PCSR 0x18 /* Peripheral Clock Status Register */
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/* 0x1c reserved */
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#define CKGR_MOR 0x20 /* Main Oscillator Register */
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#define CKGR_MCFR 0x24 /* Main Clock Frequency Register */
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#define CKGR_PLLAR 0x28 /* PLL A Register */
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#define CKGR_PLLBR 0x2c /* PLL B Register */
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#define PMC_MCKR 0x30 /* Master Clock Register */
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/* 0x34 reserved */
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/* 0x38 reserved */
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/* 0x3c reserved */
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#define PMC_PCK0 0x40 /* Programmable Clock 0 Register */
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#define PMC_PCK1 0x44 /* Programmable Clock 1 Register */
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#define PMC_PCK2 0x48 /* Programmable Clock 2 Register */
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#define PMC_PCK3 0x4c /* Programmable Clock 3 Register */
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/* 0x50 reserved */
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/* 0x54 reserved */
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/* 0x58 reserved */
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/* 0x5c reserved */
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#define PMC_IER 0x60 /* Interrupt Enable Register */
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#define PMC_IDR 0x64 /* Interrupt Disable Register */
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#define PMC_SR 0x68 /* Status Register */
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#define PMC_IMR 0x6c /* Interrupt Mask Register */
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/* PMC System Clock Enable Register */
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/* PMC System Clock Disable Register */
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/* PMC System Clock StatusRegister */
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#define PMC_SCER_PCK (1UL << 0) /* PCK: Processor Clock Enable */
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#define PMC_SCER_UDP (1UL << 1) /* UDP: USB Device Port Clock Enable */
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#define PMC_SCER_MCKUDP (1UL << 2) /* MCKUDP: Master disable susp/res */
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#define PMC_SCER_UHP (1UL << 4) /* UHP: USB Host Port Clock Enable */
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#define PMC_SCER_PCK0 (1UL << 8) /* PCK0: Programmable Clock out en */
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#define PMC_SCER_PCK1 (1UL << 10) /* PCK1: Programmable Clock out en */
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#define PMC_SCER_PCK2 (1UL << 11) /* PCK2: Programmable Clock out en */
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#define PMC_SCER_PCK3 (1UL << 12) /* PCK3: Programmable Clock out en */
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/* PMC Peripheral Clock Enable Register */
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/* PMC Peripheral Clock Disable Register */
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/* PMC Peripheral Clock Status Register */
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/* Each bit here is 1 << peripheral number to enable/disable/status */
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/* PMC Clock Generator Main Oscillator Register */
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#define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */
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#define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */
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#define CKGR_MOR_OSCOUNT(x) (x << 8) /* Main Oscillator Start-up Time */
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/* PMC Clock Generator Main Clock Frequency Register */
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#define CKGR_MCFR_MAINRDY (1UL << 16) /* Main Clock Ready */
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#define CKGR_MCFR_MAINF_MASK 0xfffful /* Main Clock Frequency */
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/* PMC Interrupt Enable Register */
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/* PMC Interrupt Disable Register */
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/* PMC Status Register */
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/* PMC Interrupt Mask Register */
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#define PMC_IER_MOSCS (1UL << 0) /* Main Oscillator Status */
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#define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */
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#define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */
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#define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */
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#define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */
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#define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */
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#define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */
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#define PMC_IER_PCK3RDY (1UL << 11) /* Programmable Clock 3 Ready */
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/*
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* PLL input frequency spec sheet says it must be between 1MHz and 32MHz,
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* but it works down as low as 100kHz, a frequency necessary for some
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* output frequencies to work.
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*/
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#define PMC_PLL_MIN_IN_FREQ 100000
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#define PMC_PLL_MAX_IN_FREQ 32000000
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/*
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* PLL Max output frequency is 240MHz. The errata says 180MHz is the max
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* for some revisions of this part. Be more permissive and optimistic.
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*/
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#define PMC_PLL_MAX_OUT_FREQ 240000000
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#define PMC_PLL_MULT_MIN 2
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#define PMC_PLL_MULT_MAX 2048
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#define PMC_PLL_SHIFT_TOL 5 /* Allow errors 1 part in 32 */
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#define PMC_PLL_FAST_THRESH 155000000
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#endif /* ARM_AT91_AT91_PMCREG_H */
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