78 lines
2.2 KiB
Plaintext
78 lines
2.2 KiB
Plaintext
/*-
|
|
* Copyright (c) 2015 John Wehle <john@feith.com>
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
* SUCH DAMAGE.
|
|
*
|
|
* $FreeBSD$
|
|
*/
|
|
|
|
/*
|
|
* The basic single core aml8726 (aka meson) uses an Amlogic interrupt
|
|
* controller, however meson.dtsi specifies GIC (which is present on
|
|
* the multicore aml8726) so we need to override things here.
|
|
*/
|
|
|
|
/include/ "meson.dtsi"
|
|
|
|
/ {
|
|
model = "Amlogic Meson3 SoC";
|
|
compatible = "amlogic,meson3";
|
|
|
|
interrupt-parent = <&pic>;
|
|
|
|
pic: pic@c1109a40 {
|
|
device_type = "interrupt-controller";
|
|
compatible = "amlogic,aml8726-pic";
|
|
reg = <0xc1109a40 128>; /* cbus 0x2690 */
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@200 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a9";
|
|
next-level-cache = <&L2>;
|
|
reg = <0x200>;
|
|
};
|
|
};
|
|
|
|
clk81: clk@0 {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
};
|
|
|
|
&gic {
|
|
status = "disabled";
|
|
};
|
|
|
|
&L2 {
|
|
interrupts = <0 61 1>;
|
|
};
|