ef2ee5d07a
The following pheripherals are supported: UART, MMC, AHCI, EHCI, PCIe, I2C, PMIC, GPIO, CPU temperature and clock. Note: The PCIe driver is pure mash at this moment. It will be reworked immediately when both D5237 and D2579 enter the current tree.
115 lines
3.7 KiB
C
115 lines
3.7 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _TEGRA_PMC_H_
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#define _TEGRA_PMC_H_
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enum tegra_suspend_mode {
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TEGRA_SUSPEND_NONE = 0,
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TEGRA_SUSPEND_LP2, /* CPU voltage off */
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TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
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TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
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};
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/* PARTIDs for powergate */
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enum tegra_powergate_id {
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TEGRA_POWERGATE_CRAIL = 0,
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TEGRA_POWERGATE_TD = 1,
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TEGRA_POWERGATE_VE = 2,
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TEGRA_POWERGATE_PCX = 3,
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TEGRA_POWERGATE_VDE = 4,
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TEGRA_POWERGATE_L2C = 5,
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TEGRA_POWERGATE_MPE = 6,
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TEGRA_POWERGATE_HEG = 7,
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TEGRA_POWERGATE_SAX = 8,
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TEGRA_POWERGATE_CE1 = 9,
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TEGRA_POWERGATE_CE2 = 10,
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TEGRA_POWERGATE_CE3 = 11,
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TEGRA_POWERGATE_CELP = 12,
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/* */
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TEGRA_POWERGATE_CE0 = 14,
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TEGRA_POWERGATE_C0NC = 15,
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TEGRA_POWERGATE_C1NC = 16,
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TEGRA_POWERGATE_SOR = 17,
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TEGRA_POWERGATE_DIS = 18,
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TEGRA_POWERGATE_DISB = 19,
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TEGRA_POWERGATE_XUSBA = 20,
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TEGRA_POWERGATE_XUSBB = 21,
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TEGRA_POWERGATE_XUSBC = 22,
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TEGRA_POWERGATE_VIC = 23,
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TEGRA_POWERGATE_IRAM = 24,
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/* */
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TEGRA_POWERGATE_3D = 32
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};
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/* PARTIDs for power rails */
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enum tegra_powerrail_id {
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TEGRA_IO_RAIL_CSIA = 0,
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TEGRA_IO_RAIL_CSIB = 1,
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TEGRA_IO_RAIL_DSI = 2,
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TEGRA_IO_RAIL_MIPI_BIAS = 3,
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TEGRA_IO_RAIL_PEX_BIAS = 4,
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TEGRA_IO_RAIL_PEX_CLK1 = 5,
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TEGRA_IO_RAIL_PEX_CLK2 = 6,
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TEGRA_IO_RAIL_USB0 = 9,
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TEGRA_IO_RAIL_USB1 = 10,
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TEGRA_IO_RAIL_USB2 = 11,
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TEGRA_IO_RAIL_USB_BIAS = 12,
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TEGRA_IO_RAIL_NAND = 13,
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TEGRA_IO_RAIL_UART = 14,
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TEGRA_IO_RAIL_BB = 15,
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TEGRA_IO_RAIL_AUDIO = 17,
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TEGRA_IO_RAIL_HSIC = 19,
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TEGRA_IO_RAIL_COMP = 22,
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TEGRA_IO_RAIL_HDMI = 28,
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TEGRA_IO_RAIL_PEX_CNTRL = 32,
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TEGRA_IO_RAIL_SDMMC1 = 33,
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TEGRA_IO_RAIL_SDMMC3 = 34,
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TEGRA_IO_RAIL_SDMMC4 = 35,
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TEGRA_IO_RAIL_CAM = 36,
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TEGRA_IO_RAIL_RES = 37,
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TEGRA_IO_RAIL_HV = 38,
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TEGRA_IO_RAIL_DSIB = 39,
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TEGRA_IO_RAIL_DSIC = 40,
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TEGRA_IO_RAIL_DSID = 41,
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TEGRA_IO_RAIL_CSIE = 44,
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TEGRA_IO_RAIL_LVDS = 57,
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TEGRA_IO_RAIL_SYS_DDC = 58,
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};
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int tegra_powergate_is_powered(enum tegra_powergate_id id);
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int tegra_powergate_power_on(enum tegra_powergate_id id);
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int tegra_powergate_power_off(enum tegra_powergate_id id);
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int tegra_powergate_remove_clamping(enum tegra_powergate_id id);
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int tegra_powergate_sequence_power_up(enum tegra_powergate_id id,
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clk_t clk, hwreset_t rst);
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int tegra_io_rail_power_on(int tegra_powerrail_id);
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int tegra_io_rail_power_off(int tegra_powerrail_id);
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#endif /*_TEGRA_PMC_H_*/ |