5b03aba6c8
files to vendor-provided ones. It should make easier to adopt platform code to new revisions of hardware and to use DTS overlays for various Beaglebone extensions (shields/capes). Original dts filenames were not changed, they're now wrappers over dts files provided by TI. So make sure you update .dtb files on your devices as part of kernel update GPIO addressing was changed: instead of one global /dev/gpioc0 there are per-bank instances of /dev/gpiocX. Each bank has 32 pins so for instance pin 121 on /dev/gpioc0 in old addressing scheme is now pin 25 on /dev/gpioc3 On Pandaboard serial console devices was changed from /dev/ttyu0 to /dev/ttyu2 so you'll have to update /etc/ttys to get login prompt on serial port in multiuser mode. Single user mode serial console should work as-is Differential Revision: https://reviews.freebsd.org/D2146 Reviewed by: rpaulo, ian, Michal Meloun, Svatopluk Kraus
446 lines
12 KiB
C
446 lines
12 KiB
C
/*
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* Copyright (c) 2010
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* Ben Gray <ben.r.gray@gmail.com>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ben Gray.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* Exposes pinmux module to pinctrl-compatible interface
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "ti_pinmux.h"
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struct pincfg {
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uint32_t reg;
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uint32_t conf;
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};
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static struct resource_spec ti_pinmux_res_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Control memory window */
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{ -1, 0 }
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};
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static struct ti_pinmux_softc *ti_pinmux_sc;
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#define ti_pinmux_read_2(sc, reg) \
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bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define ti_pinmux_write_2(sc, reg, val) \
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bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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#define ti_pinmux_read_4(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define ti_pinmux_write_4(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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/**
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* ti_padconf_devmap - Array of pins, should be defined one per SoC
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*
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* This array is typically defined in one of the targeted *_scm_pinumx.c
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* files and is specific to the given SoC platform. Each entry in the array
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* corresponds to an individual pin.
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*/
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extern const struct ti_pinmux_device ti_pinmux_dev;
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/**
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* ti_pinmux_padconf_from_name - searches the list of pads and returns entry
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* with matching ball name.
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* @ballname: the name of the ball
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*
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* RETURNS:
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* A pointer to the matching padconf or NULL if the ball wasn't found.
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*/
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static const struct ti_pinmux_padconf*
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ti_pinmux_padconf_from_name(const char *ballname)
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{
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const struct ti_pinmux_padconf *padconf;
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padconf = ti_pinmux_dev.padconf;
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while (padconf->ballname != NULL) {
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if (strcmp(ballname, padconf->ballname) == 0)
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return(padconf);
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padconf++;
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}
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return (NULL);
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}
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/**
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* ti_pinmux_padconf_set_internal - sets the muxmode and state for a pad/pin
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* @padconf: pointer to the pad structure
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* @muxmode: the name of the mode to use for the pin, i.e. "uart1_rx"
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* @state: the state to put the pad/pin in, i.e. PADCONF_PIN_???
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*
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*
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* LOCKING:
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* Internally locks it's own context.
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*
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* RETURNS:
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* 0 on success.
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* EINVAL if pin requested is outside valid range or already in use.
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*/
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static int
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ti_pinmux_padconf_set_internal(struct ti_pinmux_softc *sc,
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const struct ti_pinmux_padconf *padconf,
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const char *muxmode, unsigned int state)
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{
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unsigned int mode;
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uint16_t reg_val;
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/* populate the new value for the PADCONF register */
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reg_val = (uint16_t)(state & ti_pinmux_dev.padconf_sate_mask);
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/* find the new mode requested */
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for (mode = 0; mode < 8; mode++) {
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if ((padconf->muxmodes[mode] != NULL) &&
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(strcmp(padconf->muxmodes[mode], muxmode) == 0)) {
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break;
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}
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}
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/* couldn't find the mux mode */
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if (mode >= 8) {
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printf("Invalid mode \"%s\"\n", muxmode);
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return (EINVAL);
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}
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/* set the mux mode */
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reg_val |= (uint16_t)(mode & ti_pinmux_dev.padconf_muxmode_mask);
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if (bootverbose)
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device_printf(sc->sc_dev, "setting internal %x for %s\n",
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reg_val, muxmode);
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/* write the register value (16-bit writes) */
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ti_pinmux_write_2(sc, padconf->reg_off, reg_val);
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return (0);
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}
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/**
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* ti_pinmux_padconf_set - sets the muxmode and state for a pad/pin
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* @padname: the name of the pad, i.e. "c12"
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* @muxmode: the name of the mode to use for the pin, i.e. "uart1_rx"
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* @state: the state to put the pad/pin in, i.e. PADCONF_PIN_???
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*
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*
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* LOCKING:
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* Internally locks it's own context.
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*
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* RETURNS:
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* 0 on success.
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* EINVAL if pin requested is outside valid range or already in use.
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*/
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int
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ti_pinmux_padconf_set(const char *padname, const char *muxmode, unsigned int state)
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{
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const struct ti_pinmux_padconf *padconf;
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if (!ti_pinmux_sc)
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return (ENXIO);
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/* find the pin in the devmap */
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padconf = ti_pinmux_padconf_from_name(padname);
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if (padconf == NULL)
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return (EINVAL);
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return (ti_pinmux_padconf_set_internal(ti_pinmux_sc, padconf, muxmode, state));
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}
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/**
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* ti_pinmux_padconf_get - gets the muxmode and state for a pad/pin
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* @padname: the name of the pad, i.e. "c12"
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* @muxmode: upon return will contain the name of the muxmode of the pin
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* @state: upon return will contain the state of the pad/pin
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*
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*
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* LOCKING:
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* Internally locks it's own context.
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*
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* RETURNS:
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* 0 on success.
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* EINVAL if pin requested is outside valid range or already in use.
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*/
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int
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ti_pinmux_padconf_get(const char *padname, const char **muxmode,
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unsigned int *state)
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{
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const struct ti_pinmux_padconf *padconf;
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uint16_t reg_val;
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if (!ti_pinmux_sc)
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return (ENXIO);
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/* find the pin in the devmap */
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padconf = ti_pinmux_padconf_from_name(padname);
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if (padconf == NULL)
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return (EINVAL);
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/* read the register value (16-bit reads) */
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reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off);
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/* save the state */
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if (state)
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*state = (reg_val & ti_pinmux_dev.padconf_sate_mask);
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/* save the mode */
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if (muxmode)
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*muxmode = padconf->muxmodes[(reg_val & ti_pinmux_dev.padconf_muxmode_mask)];
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return (0);
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}
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/**
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* ti_pinmux_padconf_set_gpiomode - converts a pad to GPIO mode.
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* @gpio: the GPIO pin number (0-195)
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* @state: the state to put the pad/pin in, i.e. PADCONF_PIN_???
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*
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*
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*
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* LOCKING:
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* Internally locks it's own context.
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*
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* RETURNS:
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* 0 on success.
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* EINVAL if pin requested is outside valid range or already in use.
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*/
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int
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ti_pinmux_padconf_set_gpiomode(uint32_t gpio, unsigned int state)
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{
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const struct ti_pinmux_padconf *padconf;
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uint16_t reg_val;
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if (!ti_pinmux_sc)
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return (ENXIO);
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/* find the gpio pin in the padconf array */
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padconf = ti_pinmux_dev.padconf;
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while (padconf->ballname != NULL) {
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if (padconf->gpio_pin == gpio)
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break;
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padconf++;
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}
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if (padconf->ballname == NULL)
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return (EINVAL);
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/* populate the new value for the PADCONF register */
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reg_val = (uint16_t)(state & ti_pinmux_dev.padconf_sate_mask);
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/* set the mux mode */
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reg_val |= (uint16_t)(padconf->gpio_mode & ti_pinmux_dev.padconf_muxmode_mask);
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/* write the register value (16-bit writes) */
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ti_pinmux_write_2(ti_pinmux_sc, padconf->reg_off, reg_val);
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return (0);
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}
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/**
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* ti_pinmux_padconf_get_gpiomode - gets the current GPIO mode of the pin
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* @gpio: the GPIO pin number (0-195)
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* @state: upon return will contain the state
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*
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*
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*
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* LOCKING:
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* Internally locks it's own context.
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*
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* RETURNS:
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* 0 on success.
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* EINVAL if pin requested is outside valid range or not configured as GPIO.
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*/
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int
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ti_pinmux_padconf_get_gpiomode(uint32_t gpio, unsigned int *state)
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{
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const struct ti_pinmux_padconf *padconf;
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uint16_t reg_val;
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if (!ti_pinmux_sc)
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return (ENXIO);
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/* find the gpio pin in the padconf array */
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padconf = ti_pinmux_dev.padconf;
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while (padconf->ballname != NULL) {
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if (padconf->gpio_pin == gpio)
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break;
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padconf++;
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}
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if (padconf->ballname == NULL)
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return (EINVAL);
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/* read the current register settings */
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reg_val = ti_pinmux_read_2(ti_pinmux_sc, padconf->reg_off);
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/* check to make sure the pins is configured as GPIO in the first state */
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if ((reg_val & ti_pinmux_dev.padconf_muxmode_mask) != padconf->gpio_mode)
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return (EINVAL);
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/* read and store the reset of the state, i.e. pull-up, pull-down, etc */
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if (state)
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*state = (reg_val & ti_pinmux_dev.padconf_sate_mask);
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return (0);
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}
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static int
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ti_pinmux_configure_pins(device_t dev, phandle_t cfgxref)
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{
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struct pincfg *cfgtuples, *cfg;
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phandle_t cfgnode;
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int i, ntuples;
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static struct ti_pinmux_softc *sc;
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sc = device_get_softc(dev);
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cfgnode = OF_node_from_xref(cfgxref);
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ntuples = OF_getencprop_alloc(cfgnode, "pinctrl-single,pins", sizeof(*cfgtuples),
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(void **)&cfgtuples);
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if (ntuples < 0)
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return (ENOENT);
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if (ntuples == 0)
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return (0); /* Empty property is not an error. */
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for (i = 0, cfg = cfgtuples; i < ntuples; i++, cfg++) {
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if (bootverbose) {
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char name[32];
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OF_getprop(cfgnode, "name", &name, sizeof(name));
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printf("%16s: muxreg 0x%04x muxval 0x%02x\n",
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name, cfg->reg, cfg->conf);
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}
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/* write the register value (16-bit writes) */
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ti_pinmux_write_2(sc, cfg->reg, cfg->conf);
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}
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free(cfgtuples, M_OFWPROP);
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return (0);
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}
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/*
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* Device part of OMAP SCM driver
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*/
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static int
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ti_pinmux_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "pinctrl-single"))
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return (ENXIO);
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if (ti_pinmux_sc) {
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printf("%s: multiple pinctrl modules in device tree data, ignoring\n",
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__func__);
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return (EEXIST);
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}
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device_set_desc(dev, "TI Pinmux Module");
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return (BUS_PROBE_DEFAULT);
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}
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/**
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* ti_pinmux_attach - attaches the pinmux to the simplebus
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* @dev: new device
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*
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* RETURNS
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* Zero on sucess or ENXIO if an error occuried.
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*/
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static int
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ti_pinmux_attach(device_t dev)
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{
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struct ti_pinmux_softc *sc = device_get_softc(dev);
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#if 0
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if (ti_pinmux_sc)
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return (ENXIO);
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#endif
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sc->sc_dev = dev;
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if (bus_alloc_resources(dev, ti_pinmux_res_spec, sc->sc_res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_res[0]);
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sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]);
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if (ti_pinmux_sc == NULL)
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ti_pinmux_sc = sc;
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fdt_pinctrl_register(dev, "pinctrl-single,pins");
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fdt_pinctrl_configure_tree(dev);
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return (0);
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}
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static device_method_t ti_pinmux_methods[] = {
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DEVMETHOD(device_probe, ti_pinmux_probe),
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DEVMETHOD(device_attach, ti_pinmux_attach),
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/* fdt_pinctrl interface */
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DEVMETHOD(fdt_pinctrl_configure, ti_pinmux_configure_pins),
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{ 0, 0 }
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};
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static driver_t ti_pinmux_driver = {
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"ti_pinmux",
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ti_pinmux_methods,
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sizeof(struct ti_pinmux_softc),
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};
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static devclass_t ti_pinmux_devclass;
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DRIVER_MODULE(ti_pinmux, simplebus, ti_pinmux_driver, ti_pinmux_devclass, 0, 0);
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