d1f7b2d7ee
chip int. and ext. clock synchronisation). Fixed workaround for transmit threshold underrun. Added volatile keyword to CSR_READ_* and CSR_WRITE_* macroses. Added DELAYs to eliminate randomness caused by processor speed. Fixed all TXCON and RXCON registers to be accessed only when chip is idle, as manual told. Changed epic_init_phy to drop link by isolating and going loopback, should should force link partner to restart autonegotiation. PR: kern/10535, kern/9742, kern/10575 Submitted by: Peter Jeremy, David Greenman |
||
---|---|---|
.. | ||
if_tx.c | ||
if_txreg.h | ||
if_txvar.h |