Ruslan Bukin 9862cef040 o Separate rtc and timecmp registers: they are different across ... RISC-V cpu implementations. o Update RocketChip device tree source (DTS). We now support latest verison of RocketChip synthesized on Xilinx FPGA (Zedboard). RocketChip is an implementation of RISC-V processor written on Chisel hardware construction language. Sponsored by: DARPA, AFRL Sponsored by: HEIF5		2016-09-01 14:58:11 +00:00
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conf	o Remove operation in machine mode.	2016-08-10 12:41:36 +00:00
include	o Remove operation in machine mode.	2016-08-10 12:41:36 +00:00
riscv	o Separate rtc and timecmp registers: they are different across	2016-09-01 14:58:11 +00:00