c283dd9dad
o do not use the in* and out* functions. These functions are used by legacy drivers and thus must have ia32 compatible behaviour. Hence, they need to have fences. Using these functions for newbus would then pessimize performance. o remove the conditional compilation of PIO and/or MEMIO support. It's a PITA without having any significant benefit. We always support them both. Since there are no I/O ports on ia64 (they are simulated by the chipset by translating memory mapped I/O to predefined uncacheable memory regions) the only difference between PIO and MEMIO is in the address calculation. There should be enough ILP that can be exploited here that making these computations compile-time conditional is not worth it. We now also don't use the read* and write* functions. o Add the missing *_8 variants. They were missing, although not missed. It's for completeness. o Do not add the fences that were present in the low-level support functions here. We're using uncacheable memory, which means that accesses are in program order. Change the barrier implementation to not only do a memory fence, but also an acceptance fence. This should more reliably synchronize drivers with the hardware. The memory fence enforces ordering, but does not imply visibility (ie the access does not necessarily have happened). This is what the acceptance deals with. cpufunc.h cleanup: o Remove the low-level memory mapped I/O support functions. They are not used. Keep the low-level I/O port access functions for legacy drivers and add fences to ensure ia32 compatibility. o Remove the syscons specific functions now that we have moved the proper definitions where they belong. o Replace the ia64_port_address() and ia64_memory_address() functions with macros. There's a bigger change inline functions get inlined when there aren't function callsi and the calculations are simply enough to do it with macros. Replace the one reference to ia64_memory address in mp_machdep.c to use the macro.
1019 lines
30 KiB
C
1019 lines
30 KiB
C
/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */
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/*-
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* Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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|
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef _MACHINE_BUS_H_
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#define _MACHINE_BUS_H_
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/*
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* Platform notes:
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* o We don't use the _MACHINE_BUS_PIO_H_ and _MACHINE_BUS_MEMIO_H_
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* macros to conditionally compile for I/O port, memory mapped I/O
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* or both. It's a micro-optimization that is not worth the pain
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* because there is no I/O port space. I/O ports are emulated by
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* doing memory mapped I/O in a special memory range. The address
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* translation is slightly magic for I/O port accesses, but it does
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* not warrant the overhead.
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*
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*/
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#define _MACHINE_BUS_MEMIO_H_
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#define _MACHINE_BUS_PIO_H_
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#include <machine/cpufunc.h>
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/*
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* Values for the ia64 bus space tag, not to be used directly by MI code.
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*/
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#define IA64_BUS_SPACE_IO 0 /* space is i/o space */
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#define IA64_BUS_SPACE_MEM 1 /* space is mem space */
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/*
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* Bus address and size types
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*/
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typedef u_long bus_addr_t;
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typedef u_long bus_size_t;
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#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF
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#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF
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#define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFF
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#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF
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#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF
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#define BUS_SPACE_MAXADDR 0xFFFFFFFF
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#define BUS_SPACE_UNRESTRICTED (~0)
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/*
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* Access methods for bus resources and address space.
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*/
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typedef int bus_space_tag_t;
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typedef u_long bus_space_handle_t;
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/*
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* Map a region of device bus space into CPU virtual address space.
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*/
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#define BUS_SPACE_MAP_CACHEABLE 0x01
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#define BUS_SPACE_MAP_LINEAR 0x02
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int
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bus_space_map(bus_space_tag_t bst, bus_addr_t addr, bus_size_t size, int flags,
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bus_space_handle_t *bshp);
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/*
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* Unmap a region of device bus space.
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*/
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static __inline void
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bus_space_unmap(bus_space_tag_t bst __unused, bus_space_handle_t bsh __unused,
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bus_size_t size __unused)
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{
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}
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/*
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* Get a new handle for a subregion of an already-mapped area of bus space.
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*/
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static __inline int
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bus_space_subregion(bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_size_t ofs, bus_size_t size, bus_space_handle_t *nbshp)
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{
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*nbshp = bsh + ofs;
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return (0);
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}
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/*
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* Allocate a region of memory that is accessible to devices in bus space.
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*/
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int
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bus_space_alloc(bus_space_tag_t bst, bus_addr_t rstart, bus_addr_t rend,
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bus_size_t size, bus_size_t align, bus_size_t boundary, int flags,
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bus_addr_t *addrp, bus_space_handle_t *bshp);
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/*
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* Free a region of bus space accessible memory.
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*/
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void
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bus_space_free(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t size);
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/*
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* Bus read/write barrier method.
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*/
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#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
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#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
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static __inline void
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bus_space_barrier(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs,
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bus_size_t size, int flags)
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{
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ia64_mf_a();
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ia64_mf();
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}
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/*
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* Read 1 unit of data from bus space described by the tag, handle and ofs
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* tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The
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* data is returned.
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*/
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static __inline uint8_t
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bus_space_read_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs)
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{
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uint8_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
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__MEMIO_ADDR(bsh + ofs);
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return (*bsp);
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}
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static __inline uint16_t
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bus_space_read_2(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs)
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{
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uint16_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
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__MEMIO_ADDR(bsh + ofs);
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return (*bsp);
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}
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static __inline uint32_t
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bus_space_read_4(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs)
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{
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uint32_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
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__MEMIO_ADDR(bsh + ofs);
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return (*bsp);
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}
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static __inline uint64_t
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bus_space_read_8(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs)
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{
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uint64_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
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__MEMIO_ADDR(bsh + ofs);
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return (*bsp);
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}
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/*
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* Write 1 unit of data to bus space described by the tag, handle and ofs
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* tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The
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* data is passed by value.
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*/
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static __inline void
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bus_space_write_1(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs,
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uint8_t val)
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{
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uint8_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
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__MEMIO_ADDR(bsh + ofs);
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*bsp = val;
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}
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static __inline void
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bus_space_write_2(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs,
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uint16_t val)
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{
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uint16_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
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__MEMIO_ADDR(bsh + ofs);
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*bsp = val;
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}
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static __inline void
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bus_space_write_4(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs,
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uint32_t val)
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{
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uint32_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
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__MEMIO_ADDR(bsh + ofs);
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*bsp = val;
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}
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static __inline void
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bus_space_write_8(bus_space_tag_t bst, bus_space_handle_t bsh, bus_size_t ofs,
|
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uint64_t val)
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{
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|
uint64_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
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__MEMIO_ADDR(bsh + ofs);
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*bsp = val;
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}
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|
|
|
|
/*
|
|
* Read count units of data from bus space described by the tag, handle and
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* ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The
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* data is returned in the buffer passed by reference.
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*/
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static __inline void
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bus_space_read_multi_1(bus_space_tag_t bst, bus_space_handle_t bsh,
|
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bus_size_t ofs, uint8_t *bufp, size_t count)
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|
{
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uint8_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
while (count-- > 0)
|
|
*bufp++ = *bsp;
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|
}
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|
|
static __inline void
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bus_space_read_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
|
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bus_size_t ofs, uint16_t *bufp, size_t count)
|
|
{
|
|
uint16_t __volatile *bsp;
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
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while (count-- > 0)
|
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*bufp++ = *bsp;
|
|
}
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|
|
static __inline void
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bus_space_read_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_size_t ofs, uint32_t *bufp, size_t count)
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{
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uint32_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
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__MEMIO_ADDR(bsh + ofs);
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while (count-- > 0)
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*bufp++ = *bsp;
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}
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|
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static __inline void
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bus_space_read_multi_8(bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_size_t ofs, uint64_t *bufp, size_t count)
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{
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|
uint64_t __volatile *bsp;
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bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
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__MEMIO_ADDR(bsh + ofs);
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while (count-- > 0)
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|
*bufp++ = *bsp;
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|
}
|
|
|
|
|
|
/*
|
|
* Write count units of data to bus space described by the tag, handle and
|
|
* ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The
|
|
* data is read from the buffer passed by reference.
|
|
*/
|
|
static __inline void
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bus_space_write_multi_1(bus_space_tag_t bst, bus_space_handle_t bsh,
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bus_size_t ofs, const uint8_t *bufp, size_t count)
|
|
{
|
|
uint8_t __volatile *bsp;
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|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
while (count-- > 0)
|
|
*bsp = *bufp++;
|
|
}
|
|
|
|
static __inline void
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|
bus_space_write_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
|
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bus_size_t ofs, const uint16_t *bufp, size_t count)
|
|
{
|
|
uint16_t __volatile *bsp;
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
while (count-- > 0)
|
|
*bsp = *bufp++;
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
|
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bus_size_t ofs, const uint32_t *bufp, size_t count)
|
|
{
|
|
uint32_t __volatile *bsp;
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
while (count-- > 0)
|
|
*bsp = *bufp++;
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_multi_8(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, const uint64_t *bufp, size_t count)
|
|
{
|
|
uint64_t __volatile *bsp;
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
while (count-- > 0)
|
|
*bsp = *bufp++;
|
|
}
|
|
|
|
|
|
/*
|
|
* Read count units of data from bus space described by the tag, handle and
|
|
* ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The
|
|
* data is written to the buffer passed by reference and read from successive
|
|
* bus space addresses. Access is unordered.
|
|
*/
|
|
static __inline void
|
|
bus_space_read_region_1(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint8_t *bufp, size_t count)
|
|
{
|
|
uint8_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bufp++ = *bsp;
|
|
ofs += 1;
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_region_2(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint16_t *bufp, size_t count)
|
|
{
|
|
uint16_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bufp++ = *bsp;
|
|
ofs += 2;
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_region_4(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint32_t *bufp, size_t count)
|
|
{
|
|
uint32_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bufp++ = *bsp;
|
|
ofs += 4;
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_read_region_8(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint64_t *bufp, size_t count)
|
|
{
|
|
uint64_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bufp++ = *bsp;
|
|
ofs += 8;
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* Write count units of data from bus space described by the tag, handle and
|
|
* ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The
|
|
* data is read from the buffer passed by reference and written to successive
|
|
* bus space addresses. Access is unordered.
|
|
*/
|
|
static __inline void
|
|
bus_space_write_region_1(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, const uint8_t *bufp, size_t count)
|
|
{
|
|
uint8_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bsp = *bufp++;
|
|
ofs += 1;
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_region_2(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, const uint16_t *bufp, size_t count)
|
|
{
|
|
uint16_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bsp = *bufp++;
|
|
ofs += 2;
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_region_4(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, const uint32_t *bufp, size_t count)
|
|
{
|
|
uint32_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bsp = *bufp++;
|
|
ofs += 4;
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_write_region_8(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, const uint64_t *bufp, size_t count)
|
|
{
|
|
uint64_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bsp = *bufp++;
|
|
ofs += 8;
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* Write count units of data from bus space described by the tag, handle and
|
|
* ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The
|
|
* data is passed by value. Writes are unordered.
|
|
*/
|
|
static __inline void
|
|
bus_space_set_multi_1(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint8_t val, size_t count)
|
|
{
|
|
uint8_t __volatile *bsp;
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
while (count-- > 0)
|
|
*bsp = val;
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_multi_2(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint16_t val, size_t count)
|
|
{
|
|
uint16_t __volatile *bsp;
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
while (count-- > 0)
|
|
*bsp = val;
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_multi_4(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint32_t val, size_t count)
|
|
{
|
|
uint32_t __volatile *bsp;
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
while (count-- > 0)
|
|
*bsp = val;
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_multi_8(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint64_t val, size_t count)
|
|
{
|
|
uint64_t __volatile *bsp;
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
while (count-- > 0)
|
|
*bsp = val;
|
|
}
|
|
|
|
|
|
/*
|
|
* Write count units of data from bus space described by the tag, handle and
|
|
* ofs tuple. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes. The
|
|
* data is passed by value and written to successive bus space addresses.
|
|
* Writes are unordered.
|
|
*/
|
|
static __inline void
|
|
bus_space_set_region_1(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint8_t val, size_t count)
|
|
{
|
|
uint8_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bsp = val;
|
|
ofs += 1;
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_region_2(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint16_t val, size_t count)
|
|
{
|
|
uint16_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bsp = val;
|
|
ofs += 2;
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_region_4(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint32_t val, size_t count)
|
|
{
|
|
uint32_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bsp = val;
|
|
ofs += 4;
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_set_region_8(bus_space_tag_t bst, bus_space_handle_t bsh,
|
|
bus_size_t ofs, uint64_t val, size_t count)
|
|
{
|
|
uint64_t __volatile *bsp;
|
|
while (count-- > 0) {
|
|
bsp = (bst == IA64_BUS_SPACE_IO) ? __PIO_ADDR(bsh + ofs) :
|
|
__MEMIO_ADDR(bsh + ofs);
|
|
*bsp = val;
|
|
ofs += 8;
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* Copy count units of data from bus space described by the tag and the first
|
|
* handle and ofs pair to bus space described by the tag and the second handle
|
|
* and ofs pair. A unit of data can be 1 byte, 2 bytes, 4 bytes or 8 bytes.
|
|
* The data is read from successive bus space addresses and also written to
|
|
* successive bus space addresses. Both reads and writes are unordered.
|
|
*/
|
|
static __inline void
|
|
bus_space_copy_region_1(bus_space_tag_t bst, bus_space_handle_t bsh1,
|
|
bus_size_t ofs1, bus_space_handle_t bsh2, bus_size_t ofs2, size_t count)
|
|
{
|
|
bus_addr_t dst, src;
|
|
uint8_t __volatile *dstp, *srcp;
|
|
src = bsh1 + ofs1;
|
|
dst = bsh2 + ofs2;
|
|
if (dst > src) {
|
|
src += count - 1;
|
|
dst += count - 1;
|
|
while (count-- > 0) {
|
|
if (bst == IA64_BUS_SPACE_IO) {
|
|
srcp = __PIO_ADDR(src);
|
|
dstp = __PIO_ADDR(dst);
|
|
} else {
|
|
srcp = __MEMIO_ADDR(src);
|
|
dstp = __MEMIO_ADDR(dst);
|
|
}
|
|
*dstp = *srcp;
|
|
src -= 1;
|
|
dst -= 1;
|
|
}
|
|
} else {
|
|
while (count-- > 0) {
|
|
if (bst == IA64_BUS_SPACE_IO) {
|
|
srcp = __PIO_ADDR(src);
|
|
dstp = __PIO_ADDR(dst);
|
|
} else {
|
|
srcp = __MEMIO_ADDR(src);
|
|
dstp = __MEMIO_ADDR(dst);
|
|
}
|
|
*dstp = *srcp;
|
|
src += 1;
|
|
dst += 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_2(bus_space_tag_t bst, bus_space_handle_t bsh1,
|
|
bus_size_t ofs1, bus_space_handle_t bsh2, bus_size_t ofs2, size_t count)
|
|
{
|
|
bus_addr_t dst, src;
|
|
uint16_t __volatile *dstp, *srcp;
|
|
src = bsh1 + ofs1;
|
|
dst = bsh2 + ofs2;
|
|
if (dst > src) {
|
|
src += (count - 1) << 1;
|
|
dst += (count - 1) << 1;
|
|
while (count-- > 0) {
|
|
if (bst == IA64_BUS_SPACE_IO) {
|
|
srcp = __PIO_ADDR(src);
|
|
dstp = __PIO_ADDR(dst);
|
|
} else {
|
|
srcp = __MEMIO_ADDR(src);
|
|
dstp = __MEMIO_ADDR(dst);
|
|
}
|
|
*dstp = *srcp;
|
|
src -= 2;
|
|
dst -= 2;
|
|
}
|
|
} else {
|
|
while (count-- > 0) {
|
|
if (bst == IA64_BUS_SPACE_IO) {
|
|
srcp = __PIO_ADDR(src);
|
|
dstp = __PIO_ADDR(dst);
|
|
} else {
|
|
srcp = __MEMIO_ADDR(src);
|
|
dstp = __MEMIO_ADDR(dst);
|
|
}
|
|
*dstp = *srcp;
|
|
src += 2;
|
|
dst += 2;
|
|
}
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_4(bus_space_tag_t bst, bus_space_handle_t bsh1,
|
|
bus_size_t ofs1, bus_space_handle_t bsh2, bus_size_t ofs2, size_t count)
|
|
{
|
|
bus_addr_t dst, src;
|
|
uint32_t __volatile *dstp, *srcp;
|
|
src = bsh1 + ofs1;
|
|
dst = bsh2 + ofs2;
|
|
if (dst > src) {
|
|
src += (count - 1) << 2;
|
|
dst += (count - 1) << 2;
|
|
while (count-- > 0) {
|
|
if (bst == IA64_BUS_SPACE_IO) {
|
|
srcp = __PIO_ADDR(src);
|
|
dstp = __PIO_ADDR(dst);
|
|
} else {
|
|
srcp = __MEMIO_ADDR(src);
|
|
dstp = __MEMIO_ADDR(dst);
|
|
}
|
|
*dstp = *srcp;
|
|
src -= 4;
|
|
dst -= 4;
|
|
}
|
|
} else {
|
|
while (count-- > 0) {
|
|
if (bst == IA64_BUS_SPACE_IO) {
|
|
srcp = __PIO_ADDR(src);
|
|
dstp = __PIO_ADDR(dst);
|
|
} else {
|
|
srcp = __MEMIO_ADDR(src);
|
|
dstp = __MEMIO_ADDR(dst);
|
|
}
|
|
*dstp = *srcp;
|
|
src += 4;
|
|
dst += 4;
|
|
}
|
|
}
|
|
}
|
|
|
|
static __inline void
|
|
bus_space_copy_region_8(bus_space_tag_t bst, bus_space_handle_t bsh1,
|
|
bus_size_t ofs1, bus_space_handle_t bsh2, bus_size_t ofs2, size_t count)
|
|
{
|
|
bus_addr_t dst, src;
|
|
uint64_t __volatile *dstp, *srcp;
|
|
src = bsh1 + ofs1;
|
|
dst = bsh2 + ofs2;
|
|
if (dst > src) {
|
|
src += (count - 1) << 3;
|
|
dst += (count - 1) << 3;
|
|
while (count-- > 0) {
|
|
if (bst == IA64_BUS_SPACE_IO) {
|
|
srcp = __PIO_ADDR(src);
|
|
dstp = __PIO_ADDR(dst);
|
|
} else {
|
|
srcp = __MEMIO_ADDR(src);
|
|
dstp = __MEMIO_ADDR(dst);
|
|
}
|
|
*dstp = *srcp;
|
|
src -= 8;
|
|
dst -= 8;
|
|
}
|
|
} else {
|
|
while (count-- > 0) {
|
|
if (bst == IA64_BUS_SPACE_IO) {
|
|
srcp = __PIO_ADDR(src);
|
|
dstp = __PIO_ADDR(dst);
|
|
} else {
|
|
srcp = __MEMIO_ADDR(src);
|
|
dstp = __MEMIO_ADDR(dst);
|
|
}
|
|
*dstp = *srcp;
|
|
src += 8;
|
|
dst += 8;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* Stream accesses are the same as normal accesses on ia64; there are no
|
|
* supported bus systems with an endianess different from the host one.
|
|
*/
|
|
#define bus_space_read_stream_1(t, h, o) \
|
|
bus_space_read_1(t, h, o)
|
|
#define bus_space_read_stream_2(t, h, o) \
|
|
bus_space_read_2(t, h, o)
|
|
#define bus_space_read_stream_4(t, h, o) \
|
|
bus_space_read_4(t, h, o)
|
|
#define bus_space_read_stream_8(t, h, o) \
|
|
bus_space_read_8(t, h, o)
|
|
|
|
#define bus_space_read_multi_stream_1(t, h, o, a, c) \
|
|
bus_space_read_multi_1(t, h, o, a, c)
|
|
#define bus_space_read_multi_stream_2(t, h, o, a, c) \
|
|
bus_space_read_multi_2(t, h, o, a, c)
|
|
#define bus_space_read_multi_stream_4(t, h, o, a, c) \
|
|
bus_space_read_multi_4(t, h, o, a, c)
|
|
#define bus_space_read_multi_stream_8(t, h, o, a, c) \
|
|
bus_space_read_multi_8(t, h, o, a, c)
|
|
|
|
#define bus_space_write_stream_1(t, h, o, v) \
|
|
bus_space_write_1(t, h, o, v)
|
|
#define bus_space_write_stream_2(t, h, o, v) \
|
|
bus_space_write_2(t, h, o, v)
|
|
#define bus_space_write_stream_4(t, h, o, v) \
|
|
bus_space_write_4(t, h, o, v)
|
|
#define bus_space_write_stream_8(t, h, o, v) \
|
|
bus_space_write_8(t, h, o, v)
|
|
|
|
#define bus_space_write_multi_stream_1(t, h, o, a, c) \
|
|
bus_space_write_multi_1(t, h, o, a, c)
|
|
#define bus_space_write_multi_stream_2(t, h, o, a, c) \
|
|
bus_space_write_multi_2(t, h, o, a, c)
|
|
#define bus_space_write_multi_stream_4(t, h, o, a, c) \
|
|
bus_space_write_multi_4(t, h, o, a, c)
|
|
#define bus_space_write_multi_stream_8(t, h, o, a, c) \
|
|
bus_space_write_multi_8(t, h, o, a, c)
|
|
|
|
#define bus_space_set_multi_stream_1(t, h, o, v, c) \
|
|
bus_space_set_multi_1(t, h, o, v, c)
|
|
#define bus_space_set_multi_stream_2(t, h, o, v, c) \
|
|
bus_space_set_multi_2(t, h, o, v, c)
|
|
#define bus_space_set_multi_stream_4(t, h, o, v, c) \
|
|
bus_space_set_multi_4(t, h, o, v, c)
|
|
#define bus_space_set_multi_stream_8(t, h, o, v, c) \
|
|
bus_space_set_multi_8(t, h, o, v, c)
|
|
|
|
#define bus_space_read_region_stream_1(t, h, o, a, c) \
|
|
bus_space_read_region_1(t, h, o, a, c)
|
|
#define bus_space_read_region_stream_2(t, h, o, a, c) \
|
|
bus_space_read_region_2(t, h, o, a, c)
|
|
#define bus_space_read_region_stream_4(t, h, o, a, c) \
|
|
bus_space_read_region_4(t, h, o, a, c)
|
|
#define bus_space_read_region_stream_8(t, h, o, a, c) \
|
|
bus_space_read_region_8(t, h, o, a, c)
|
|
|
|
#define bus_space_write_region_stream_1(t, h, o, a, c) \
|
|
bus_space_write_region_1(t, h, o, a, c)
|
|
#define bus_space_write_region_stream_2(t, h, o, a, c) \
|
|
bus_space_write_region_2(t, h, o, a, c)
|
|
#define bus_space_write_region_stream_4(t, h, o, a, c) \
|
|
bus_space_write_region_4(t, h, o, a, c)
|
|
#define bus_space_write_region_stream_8(t, h, o, a, c) \
|
|
bus_space_write_region_8(t, h, o, a, c)
|
|
|
|
#define bus_space_set_region_stream_1(t, h, o, v, c) \
|
|
bus_space_set_region_1(t, h, o, v, c)
|
|
#define bus_space_set_region_stream_2(t, h, o, v, c) \
|
|
bus_space_set_region_2(t, h, o, v, c)
|
|
#define bus_space_set_region_stream_4(t, h, o, v, c) \
|
|
bus_space_set_region_4(t, h, o, v, c)
|
|
#define bus_space_set_region_stream_8(t, h, o, v, c) \
|
|
bus_space_set_region_8(t, h, o, v, c)
|
|
|
|
#define bus_space_copy_region_stream_1(t, h1, o1, h2, o2, c) \
|
|
bus_space_copy_region_1(t, h1, o1, h2, o2, c)
|
|
#define bus_space_copy_region_stream_2(t, h1, o1, h2, o2, c) \
|
|
bus_space_copy_region_2(t, h1, o1, h2, o2, c)
|
|
#define bus_space_copy_region_stream_4(t, h1, o1, h2, o2, c) \
|
|
bus_space_copy_region_4(t, h1, o1, h2, o2, c)
|
|
#define bus_space_copy_region_stream_8(t, h1, o1, h2, o2, c) \
|
|
bus_space_copy_region_8(t, h1, o1, h2, o2, c)
|
|
|
|
|
|
/*
|
|
* Flags used in various bus DMA methods.
|
|
*/
|
|
#define BUS_DMA_WAITOK 0x00 /* safe to sleep (pseudo-flag) */
|
|
#define BUS_DMA_NOWAIT 0x01 /* not safe to sleep */
|
|
#define BUS_DMA_ALLOCNOW 0x02 /* perform resource allocation now */
|
|
#define BUS_DMAMEM_NOSYNC 0x04 /* map memory to not require sync */
|
|
#define BUS_DMA_ISA 0x10 /* map memory for ISA dma */
|
|
#define BUS_DMA_BUS2 0x20 /* placeholders for bus functions... */
|
|
#define BUS_DMA_BUS3 0x40
|
|
#define BUS_DMA_BUS4 0x80
|
|
|
|
/* Forwards needed by prototypes below. */
|
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struct mbuf;
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struct uio;
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/*
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* Operations performed by bus_dmamap_sync().
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*/
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#define BUS_DMASYNC_PREREAD 1
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#define BUS_DMASYNC_POSTREAD 2
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#define BUS_DMASYNC_PREWRITE 4
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#define BUS_DMASYNC_POSTWRITE 8
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/*
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* bus_dma_tag_t
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*
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* A machine-dependent opaque type describing the characteristics
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* of how to perform DMA mappings. This structure encapsultes
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* information concerning address and alignment restrictions, number
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* of S/G segments, amount of data per S/G segment, etc.
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*/
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typedef struct bus_dma_tag *bus_dma_tag_t;
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/*
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* bus_dmamap_t
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*
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* DMA mapping instance information.
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*/
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typedef struct bus_dmamap *bus_dmamap_t;
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/*
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* bus_dma_segment_t
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*
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* Describes a single contiguous DMA transaction. Values
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* are suitable for programming into DMA registers.
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*/
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typedef struct bus_dma_segment {
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bus_addr_t ds_addr; /* DMA address */
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bus_size_t ds_len; /* length of transfer */
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} bus_dma_segment_t;
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/*
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* A function that returns 1 if the address cannot be accessed by
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* a device and 0 if it can be.
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*/
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typedef int bus_dma_filter_t(void *, bus_addr_t);
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/*
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* Allocate a device specific dma_tag encapsulating the constraints of
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* the parent tag in addition to other restrictions specified:
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*
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* alignment: alignment for segments.
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* boundary: Boundary that segments cannot cross.
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* lowaddr: Low restricted address that cannot appear in a mapping.
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* highaddr: High restricted addr. that cannot appear in a mapping.
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* filtfunc: An optional function to further test if an address
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* within the range of lowaddr and highaddr cannot appear
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* in a mapping.
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* filtfuncarg: An argument that will be passed to filtfunc in addition
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* to the address to test.
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* maxsize: Maximum mapping size supported by this tag.
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* nsegments: Number of discontinuities allowed in maps.
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* maxsegsz: Maximum size of a segment in the map.
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* flags: Bus DMA flags.
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* dmat: A pointer to set to a valid dma tag should the return
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* value of this function indicate success.
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*/
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/* XXX Should probably allow specification of alignment */
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int bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignemnt,
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bus_size_t boundary, bus_addr_t lowaddr, bus_addr_t highaddr,
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bus_dma_filter_t *filtfunc, void *filtfuncarg, bus_size_t maxsize,
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int nsegments, bus_size_t maxsegsz, int flags, bus_dma_tag_t *dmat);
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int bus_dma_tag_destroy(bus_dma_tag_t dmat);
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/*
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* Allocate a handle for mapping from kva/uva/physical
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* address space into bus device space.
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*/
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int bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp);
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/*
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* Destroy a handle for mapping from kva/uva/physical
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* address space into bus device space.
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*/
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int bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map);
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/*
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* Allocate a piece of memory that can be efficiently mapped into
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* bus device space based on the constraints lited in the dma tag.
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* A dmamap to for use with dmamap_load is also allocated.
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*/
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int bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags,
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bus_dmamap_t *mapp);
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/*
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* Free a piece of memory and it's allociated dmamap, that was allocated
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* via bus_dmamem_alloc.
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*/
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void bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map);
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/*
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* A function that processes a successfully loaded dma map or an error
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* from a delayed load map.
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*/
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typedef void bus_dmamap_callback_t(void *, bus_dma_segment_t *, int, int);
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/*
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* Map the buffer buf into bus space using the dmamap map.
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*/
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int bus_dmamap_load(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf,
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bus_size_t buflen, bus_dmamap_callback_t *callback, void *callback_arg,
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int flags);
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/*
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* Like bus_dmamap_callback but includes map size in bytes. This is
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* defined as a separate interface to maintain compatiiblity for users
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* of bus_dmamap_callback_t--at some point these interfaces should be merged.
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*/
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typedef void bus_dmamap_callback2_t(void *, bus_dma_segment_t *, int,
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bus_size_t, int);
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/*
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* Like bus_dmamap_load but for mbufs. Note the use of the
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* bus_dmamap_callback2_t interface.
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*/
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int bus_dmamap_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map,
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struct mbuf *mbuf, bus_dmamap_callback2_t *callback, void *callback_arg,
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int flags);
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/*
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* Like bus_dmamap_load but for uios. Note the use of the
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* bus_dmamap_callback2_t interface.
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*/
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int bus_dmamap_load_uio(bus_dma_tag_t dmat, bus_dmamap_t map, struct uio *ui,
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bus_dmamap_callback2_t *callback, void *callback_arg, int flags);
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/*
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* Perform a syncronization operation on the given map.
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*/
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void _bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, int);
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static __inline void
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bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t dmamap, int op)
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{
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if ((dmamap) != NULL)
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_bus_dmamap_sync(dmat, dmamap, op);
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}
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/*
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* Release the mapping held by map.
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*/
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void _bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map);
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static __inline void
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bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t dmamap)
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{
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if ((dmamap) != NULL)
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_bus_dmamap_unload(dmat, dmamap);
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}
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#endif /* _MACHINE_BUS_H_ */
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