718cf2ccb9
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375 lines
9.6 KiB
C
375 lines
9.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2005, M. Warner Losh
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* All rights reserved.
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* Copyright (c) 1995, David Greenman
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ed.h"
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#ifdef ED_3C503
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/syslog.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_var.h> /* XXX: ed_3c503_mediachg() */
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#include <net/if_arp.h>
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#include <net/if_dl.h>
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#include <net/if_mib.h>
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#include <net/if_media.h>
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#include <net/bpf.h>
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#include <dev/ed/if_edreg.h>
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#include <dev/ed/if_edvar.h>
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static void ed_3c503_mediachg(struct ed_softc *sc);
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/*
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* Probe and vendor-specific initialization routine for 3Com 3c503 boards
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*/
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int
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ed_probe_3Com(device_t dev, int port_rid, int flags)
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{
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struct ed_softc *sc = device_get_softc(dev);
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int error;
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int i;
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u_int memsize;
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u_char isa16bit;
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rman_res_t conf_maddr, conf_msize, irq, junk, pmem;
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error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
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if (error)
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return (error);
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sc->asic_offset = ED_3COM_ASIC_OFFSET;
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sc->nic_offset = ED_3COM_NIC_OFFSET;
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/*
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* Verify that the kernel configured I/O address matches the board
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* configured address
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*/
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switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
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case ED_3COM_BCFR_300:
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if (rman_get_start(sc->port_res) != 0x300)
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return (ENXIO);
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break;
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case ED_3COM_BCFR_310:
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if (rman_get_start(sc->port_res) != 0x310)
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return (ENXIO);
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break;
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case ED_3COM_BCFR_330:
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if (rman_get_start(sc->port_res) != 0x330)
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return (ENXIO);
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break;
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case ED_3COM_BCFR_350:
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if (rman_get_start(sc->port_res) != 0x350)
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return (ENXIO);
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break;
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case ED_3COM_BCFR_250:
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if (rman_get_start(sc->port_res) != 0x250)
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return (ENXIO);
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break;
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case ED_3COM_BCFR_280:
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if (rman_get_start(sc->port_res) != 0x280)
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return (ENXIO);
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break;
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case ED_3COM_BCFR_2A0:
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if (rman_get_start(sc->port_res) != 0x2a0)
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return (ENXIO);
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break;
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case ED_3COM_BCFR_2E0:
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if (rman_get_start(sc->port_res) != 0x2e0)
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return (ENXIO);
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break;
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default:
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return (ENXIO);
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}
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error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
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&conf_maddr, &conf_msize);
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if (error)
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return (error);
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/*
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* Verify that the kernel shared memory address matches the board
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* configured address.
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*/
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switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
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case ED_3COM_PCFR_DC000:
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if (conf_maddr != 0xdc000)
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return (ENXIO);
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break;
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case ED_3COM_PCFR_D8000:
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if (conf_maddr != 0xd8000)
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return (ENXIO);
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break;
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case ED_3COM_PCFR_CC000:
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if (conf_maddr != 0xcc000)
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return (ENXIO);
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break;
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case ED_3COM_PCFR_C8000:
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if (conf_maddr != 0xc8000)
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return (ENXIO);
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break;
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default:
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return (ENXIO);
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}
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/*
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* Reset NIC and ASIC. Enable on-board transceiver throughout reset
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* sequence because it'll lock up if the cable isn't connected if we
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* don't.
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*/
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ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
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/*
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* Wait for a while, then un-reset it
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*/
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DELAY(50);
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/*
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* The 3Com ASIC defaults to rather strange settings for the CR after
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* a reset - it's important to set it again after the following outb
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* (this is done when we map the PROM below).
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*/
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ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
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/*
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* Wait a bit for the NIC to recover from the reset
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*/
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DELAY(5000);
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sc->vendor = ED_VENDOR_3COM;
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sc->type_str = "3c503";
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sc->mem_shared = 1;
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sc->cr_proto = ED_CR_RD2;
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/*
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* Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
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* to it.
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*/
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memsize = 8192;
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/*
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* Get station address from on-board ROM
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*/
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/*
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* First, map ethernet address PROM over the top of where the NIC
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* registers normally appear.
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*/
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ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
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for (i = 0; i < ETHER_ADDR_LEN; ++i)
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sc->enaddr[i] = ed_nic_inb(sc, i);
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/*
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* Unmap PROM - select NIC registers. The proper setting of the
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* tranceiver is set in ed_init so that the attach code is given a
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* chance to set the default based on a compile-time config option
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*/
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ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
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/*
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* Determine if this is an 8bit or 16bit board
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*/
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/*
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* select page 0 registers
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*/
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_0 | ED_CR_RD2 | ED_CR_STP);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/*
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* Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
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* board.
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*/
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ed_nic_outb(sc, ED_P0_DCR, 0);
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/*
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* select page 2 registers
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*/
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
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ed_nic_barrier(sc, ED_P0_CR, 1,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/*
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* The 3c503 forces the WTS bit to a one if this is a 16bit board
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*/
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if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
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isa16bit = 1;
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else
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isa16bit = 0;
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/*
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* select page 0 registers
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*/
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ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
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error = ed_alloc_memory(dev, 0, memsize);
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if (error)
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return (error);
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pmem = rman_get_start(sc->mem_res);
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error = ed_isa_mem_ok(dev, pmem, memsize);
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if (error)
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return (error);
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sc->mem_start = 0;
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sc->mem_size = memsize;
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sc->mem_end = sc->mem_start + memsize;
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/*
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* We have an entire 8k window to put the transmit buffers on the
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* 16bit boards. But since the 16bit 3c503's shared memory is only
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* fast enough to overlap the loading of one full-size packet, trying
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* to load more than 2 buffers can actually leave the transmitter idle
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* during the load. So 2 seems the best value. (Although a mix of
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* variable-sized packets might change this assumption. Nonetheless,
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* we optimize for linear transfers of same-size packets.)
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*/
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if (isa16bit) {
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if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
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sc->txb_cnt = 1;
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else
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sc->txb_cnt = 2;
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sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
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sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
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sc->rec_page_stop = memsize / ED_PAGE_SIZE +
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ED_3COM_RX_PAGE_OFFSET_16BIT;
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sc->mem_ring = sc->mem_start;
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} else {
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sc->txb_cnt = 1;
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sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
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sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
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sc->rec_page_stop = memsize / ED_PAGE_SIZE +
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ED_3COM_TX_PAGE_OFFSET_8BIT;
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sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
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}
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sc->isa16bit = isa16bit;
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/*
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* Initialize GA page start/stop registers. Probably only needed if
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* doing DMA, but what the hell.
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*/
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ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
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ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
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/*
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* Set IRQ. 3c503 only allows a choice of irq 2-5.
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*/
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error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
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if (error)
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return (error);
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switch (irq) {
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case 2:
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case 9:
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ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
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break;
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case 3:
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ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
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break;
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case 4:
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ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
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break;
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case 5:
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ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
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break;
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default:
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device_printf(dev, "Invalid irq configuration (%jd) must be 3-5,9 for 3c503\n",
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irq);
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return (ENXIO);
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}
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/*
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* Initialize GA configuration register. Set bank and enable shared
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* mem.
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*/
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ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
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ED_3COM_GACFR_MBS0);
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/*
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* Initialize "Vector Pointer" registers. These gawd-awful things are
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* compared to 20 bits of the address on ISA, and if they match, the
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* shared memory is disabled. We set them to 0xffff0...allegedly the
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* reset vector.
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*/
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ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
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ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
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ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
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error = ed_clear_memory(dev);
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if (error == 0) {
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sc->sc_mediachg = ed_3c503_mediachg;
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sc->sc_write_mbufs = ed_shmem_write_mbufs;
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}
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return (error);
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}
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static void
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ed_3c503_mediachg(struct ed_softc *sc)
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{
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struct ifnet *ifp = sc->ifp;
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/*
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* If this is a 3Com board, the tranceiver must be software enabled
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* (there is no settable hardware default).
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*/
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if (ifp->if_flags & IFF_LINK2)
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ed_asic_outb(sc, ED_3COM_CR, 0);
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else
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ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
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}
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#endif /* ED_3C503 */
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