a1f8ad145e
applied to our copy of llvm/clang. These can be applied in alphabetical order to a pristine llvm/clang 3.4 release source tree, to result in the same version used in FreeBSD. This is intended to clearly document all the changes until now, which mostly consist of cherry pickings from the respective upstream trunks, plus a number of hand-written FreeBSD-specific ones. Hopefully those can eventually be cleaned up and sent upstream too. MFC after: 1 week X-MFC-With: r263313
845 lines
26 KiB
Diff
845 lines
26 KiB
Diff
Pull in r198484 from upstream llvm trunk (by Venkatraman Govindaraju):
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[Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.
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Introduced here: http://svn.freebsd.org/changeset/base/262261
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Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
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===================================================================
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--- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
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+++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
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@@ -123,13 +123,18 @@ extern "C" void LLVMInitializeSparcTargetMC() {
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo);
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+ TargetRegistry::RegisterMCInstrInfo(TheSparcV9Target, createSparcMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheSparcTarget, createSparcMCRegisterInfo);
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+ TargetRegistry::RegisterMCRegInfo(TheSparcV9Target,
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+ createSparcMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget,
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createSparcMCSubtargetInfo);
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+ TargetRegistry::RegisterMCSubtargetInfo(TheSparcV9Target,
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+ createSparcMCSubtargetInfo);
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TargetRegistry::RegisterAsmStreamer(TheSparcTarget,
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createMCAsmStreamer);
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Index: lib/Target/Sparc/LLVMBuild.txt
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===================================================================
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--- lib/Target/Sparc/LLVMBuild.txt
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+++ lib/Target/Sparc/LLVMBuild.txt
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@@ -16,7 +16,7 @@
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;===------------------------------------------------------------------------===;
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[common]
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-subdirectories = InstPrinter MCTargetDesc TargetInfo
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+subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo
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[component_0]
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type = TargetGroup
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Index: lib/Target/Sparc/SparcInstrInfo.td
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===================================================================
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--- lib/Target/Sparc/SparcInstrInfo.td
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+++ lib/Target/Sparc/SparcInstrInfo.td
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@@ -76,13 +76,25 @@ def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr
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def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
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// Address operands
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+def SparcMEMrrAsmOperand : AsmOperandClass {
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+ let Name = "MEMrr";
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+ let ParserMethod = "parseMEMrrOperand";
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+}
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+
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+def SparcMEMriAsmOperand : AsmOperandClass {
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+ let Name = "MEMri";
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+ let ParserMethod = "parseMEMriOperand";
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+}
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+
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def MEMrr : Operand<iPTR> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, ptr_rc);
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+ let ParserMatchClass = SparcMEMrrAsmOperand;
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}
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def MEMri : Operand<iPTR> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, i32imm);
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+ let ParserMatchClass = SparcMEMriAsmOperand;
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}
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def TLSSym : Operand<iPTR>;
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@@ -239,7 +251,10 @@ multiclass F3_12np<string OpcStr, bits<6> Op3Val>
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// Pseudo instructions.
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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- : InstSP<outs, ins, asmstr, pattern>;
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+ : InstSP<outs, ins, asmstr, pattern> {
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+ let isCodeGenOnly = 1;
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+ let isPseudo = 1;
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+}
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// GETPCX for PIC
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let Defs = [O7] in {
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@@ -503,7 +518,7 @@ defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i3
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defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
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// "LEA" forms of add (patterns to make tblgen happy)
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-let Predicates = [Is32Bit] in
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+let Predicates = [Is32Bit], isCodeGenOnly = 1 in
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def LEA_ADDri : F3_2<2, 0b000000,
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(outs IntRegs:$dst), (ins MEMri:$addr),
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"add ${addr:arith}, $dst",
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Index: lib/Target/Sparc/CMakeLists.txt
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===================================================================
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--- lib/Target/Sparc/CMakeLists.txt
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+++ lib/Target/Sparc/CMakeLists.txt
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@@ -4,6 +4,7 @@ tablegen(LLVM SparcGenRegisterInfo.inc -gen-regist
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tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM SparcGenCodeEmitter.inc -gen-emitter)
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tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
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+tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM SparcGenSubtargetInfo.inc -gen-subtarget)
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tablegen(LLVM SparcGenCallingConv.inc -gen-callingconv)
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@@ -31,3 +32,4 @@ add_dependencies(LLVMSparcCodeGen SparcCommonTable
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(InstPrinter)
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+add_subdirectory(AsmParser)
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Index: lib/Target/Sparc/Makefile
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===================================================================
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--- lib/Target/Sparc/Makefile
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+++ lib/Target/Sparc/Makefile
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@@ -13,11 +13,12 @@ TARGET = Sparc
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
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- SparcGenAsmWriter.inc SparcGenDAGISel.inc \
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+ SparcGenAsmWriter.inc SparcGenAsmMatcher.inc \
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+ SparcGenDAGISel.inc \
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SparcGenSubtargetInfo.inc SparcGenCallingConv.inc \
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SparcGenCodeEmitter.inc
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-DIRS = InstPrinter TargetInfo MCTargetDesc
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+DIRS = InstPrinter AsmParser TargetInfo MCTargetDesc
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include $(LEVEL)/Makefile.common
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Index: lib/Target/Sparc/Sparc.td
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===================================================================
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--- lib/Target/Sparc/Sparc.td
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+++ lib/Target/Sparc/Sparc.td
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@@ -44,6 +44,10 @@ include "SparcInstrInfo.td"
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def SparcInstrInfo : InstrInfo;
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+def SparcAsmParser : AsmParser {
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+ bit ShouldEmitMatchRegisterName = 0;
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+}
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+
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//===----------------------------------------------------------------------===//
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// SPARC processors supported.
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//===----------------------------------------------------------------------===//
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@@ -77,6 +81,7 @@ def SparcAsmWriter : AsmWriter {
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def Sparc : Target {
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// Pull in Instruction Info:
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let InstructionSet = SparcInstrInfo;
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+ let AssemblyParsers = [SparcAsmParser];
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let AssemblyWriters = [SparcAsmWriter];
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}
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Index: lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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===================================================================
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--- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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@@ -0,0 +1,614 @@
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+//===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
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+//
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+// The LLVM Compiler Infrastructure
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+//
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+// This file is distributed under the University of Illinois Open Source
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+// License. See LICENSE.TXT for details.
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+//
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+//===----------------------------------------------------------------------===//
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+
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+#include "MCTargetDesc/SparcMCTargetDesc.h"
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+#include "llvm/ADT/STLExtras.h"
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+#include "llvm/MC/MCContext.h"
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+#include "llvm/MC/MCInst.h"
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+#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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+#include "llvm/MC/MCStreamer.h"
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+#include "llvm/MC/MCSubtargetInfo.h"
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+#include "llvm/MC/MCTargetAsmParser.h"
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+#include "llvm/Support/TargetRegistry.h"
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+
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+using namespace llvm;
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+
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+// The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
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+// namespace. But SPARC backend uses "SP" as its namespace.
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+namespace llvm {
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+ namespace Sparc {
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+ using namespace SP;
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+ }
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+}
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+
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+namespace {
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+class SparcAsmParser : public MCTargetAsmParser {
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+
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+ MCSubtargetInfo &STI;
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+ MCAsmParser &Parser;
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+
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+ /// @name Auto-generated Match Functions
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+ /// {
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+
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+#define GET_ASSEMBLER_HEADER
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+#include "SparcGenAsmMatcher.inc"
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+
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+ /// }
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+
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+ // public interface of the MCTargetAsmParser.
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+ bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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+ SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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+ MCStreamer &Out, unsigned &ErrorInfo,
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+ bool MatchingInlineAsm);
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+ bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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+ bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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+ SMLoc NameLoc,
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+ SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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+ bool ParseDirective(AsmToken DirectiveID);
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+
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+
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+ // Custom parse functions for Sparc specific operands.
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+ OperandMatchResultTy
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+ parseMEMrrOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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+ OperandMatchResultTy
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+ parseMEMriOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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+
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+ OperandMatchResultTy
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+ parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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+ int ImmOffsetOrReg);
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+
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+ OperandMatchResultTy
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+ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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+ StringRef Name);
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+
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+ // returns true if Tok is matched to a register and returns register in RegNo.
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+ bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo, bool isDFP,
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+ bool isQFP);
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+
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+public:
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+ SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
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+ const MCInstrInfo &MII)
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+ : MCTargetAsmParser(), STI(sti), Parser(parser) {
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+ // Initialize the set of available features.
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+ setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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+ }
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+
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+};
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+
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+ static unsigned IntRegs[32] = {
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+ Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
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+ Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
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+ Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
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+ Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
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+ Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
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+ Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
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+ Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
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+ Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
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+
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+ static unsigned FloatRegs[32] = {
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+ Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
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+ Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
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+ Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
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+ Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
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+ Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
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+ Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
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+ Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
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+ Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
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+
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+ static unsigned DoubleRegs[32] = {
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+ Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
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+ Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
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+ Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
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+ Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
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+ Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
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+ Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
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+ Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
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+ Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
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+
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+ static unsigned QuadFPRegs[32] = {
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+ Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
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+ Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
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+ Sparc::Q8, Sparc::Q7, Sparc::Q8, Sparc::Q9,
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+ Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
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+
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+
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+/// SparcOperand - Instances of this class represent a parsed Sparc machine
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+/// instruction.
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+class SparcOperand : public MCParsedAsmOperand {
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+public:
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+ enum RegisterKind {
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+ rk_None,
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+ rk_IntReg,
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+ rk_FloatReg,
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+ rk_DoubleReg,
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+ rk_QuadReg,
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+ rk_CCReg,
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+ rk_Y
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+ };
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+private:
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+ enum KindTy {
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+ k_Token,
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+ k_Register,
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+ k_Immediate,
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+ k_MemoryReg,
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+ k_MemoryImm
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+ } Kind;
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+
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+ SMLoc StartLoc, EndLoc;
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+
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+ SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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+
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+ struct Token {
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+ const char *Data;
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+ unsigned Length;
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+ };
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+
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+ struct RegOp {
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+ unsigned RegNum;
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+ RegisterKind Kind;
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+ };
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+
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+ struct ImmOp {
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+ const MCExpr *Val;
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+ };
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+
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+ struct MemOp {
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+ unsigned Base;
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+ unsigned OffsetReg;
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+ const MCExpr *Off;
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+ };
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+
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+ union {
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+ struct Token Tok;
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+ struct RegOp Reg;
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+ struct ImmOp Imm;
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+ struct MemOp Mem;
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+ };
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+public:
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+ bool isToken() const { return Kind == k_Token; }
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+ bool isReg() const { return Kind == k_Register; }
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+ bool isImm() const { return Kind == k_Immediate; }
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+ bool isMem() const { return isMEMrr() || isMEMri(); }
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+ bool isMEMrr() const { return Kind == k_MemoryReg; }
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+ bool isMEMri() const { return Kind == k_MemoryImm; }
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+
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+ StringRef getToken() const {
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+ assert(Kind == k_Token && "Invalid access!");
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+ return StringRef(Tok.Data, Tok.Length);
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+ }
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+
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+ unsigned getReg() const {
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+ assert((Kind == k_Register) && "Invalid access!");
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+ return Reg.RegNum;
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+ }
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+
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+ const MCExpr *getImm() const {
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+ assert((Kind == k_Immediate) && "Invalid access!");
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+ return Imm.Val;
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+ }
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+
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+ unsigned getMemBase() const {
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+ assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
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+ return Mem.Base;
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+ }
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+
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+ unsigned getMemOffsetReg() const {
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+ assert((Kind == k_MemoryReg) && "Invalid access!");
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+ return Mem.OffsetReg;
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+ }
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+
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+ const MCExpr *getMemOff() const {
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+ assert((Kind == k_MemoryImm) && "Invalid access!");
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+ return Mem.Off;
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+ }
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+
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+ /// getStartLoc - Get the location of the first token of this operand.
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+ SMLoc getStartLoc() const {
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+ return StartLoc;
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+ }
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+ /// getEndLoc - Get the location of the last token of this operand.
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+ SMLoc getEndLoc() const {
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+ return EndLoc;
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+ }
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+
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+ virtual void print(raw_ostream &OS) const {
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+ switch (Kind) {
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+ case k_Token: OS << "Token: " << getToken() << "\n"; break;
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+ case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
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+ case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
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+ case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
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+ << getMemOffsetReg() << "\n"; break;
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+ case k_MemoryImm: assert(getMemOff() != 0);
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+ OS << "Mem: " << getMemBase()
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+ << "+" << *getMemOff()
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+ << "\n"; break;
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+ }
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+ }
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+
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+ void addRegOperands(MCInst &Inst, unsigned N) const {
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+ assert(N == 1 && "Invalid number of operands!");
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+ Inst.addOperand(MCOperand::CreateReg(getReg()));
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+ }
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+
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+ void addImmOperands(MCInst &Inst, unsigned N) const {
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+ assert(N == 1 && "Invalid number of operands!");
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+ const MCExpr *Expr = getImm();
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+ addExpr(Inst, Expr);
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+ }
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+
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+ void addExpr(MCInst &Inst, const MCExpr *Expr) const{
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+ // Add as immediate when possible. Null MCExpr = 0.
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+ if (Expr == 0)
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+ Inst.addOperand(MCOperand::CreateImm(0));
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+ else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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+ Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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+ else
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+ Inst.addOperand(MCOperand::CreateExpr(Expr));
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+ }
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+
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+ void addMEMrrOperands(MCInst &Inst, unsigned N) const {
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+ assert(N == 2 && "Invalid number of operands!");
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+
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+ Inst.addOperand(MCOperand::CreateReg(getMemBase()));
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+
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+ assert(getMemOffsetReg() != 0 && "Invalid offset");
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+ Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg()));
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+ }
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+
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+ void addMEMriOperands(MCInst &Inst, unsigned N) const {
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+ assert(N == 2 && "Invalid number of operands!");
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+
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+ Inst.addOperand(MCOperand::CreateReg(getMemBase()));
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+
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+ const MCExpr *Expr = getMemOff();
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+ addExpr(Inst, Expr);
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+ }
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+
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+ static SparcOperand *CreateToken(StringRef Str, SMLoc S) {
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+ SparcOperand *Op = new SparcOperand(k_Token);
|
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+ Op->Tok.Data = Str.data();
|
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+ Op->Tok.Length = Str.size();
|
|
+ Op->StartLoc = S;
|
|
+ Op->EndLoc = S;
|
|
+ return Op;
|
|
+ }
|
|
+
|
|
+ static SparcOperand *CreateReg(unsigned RegNum,
|
|
+ SparcOperand::RegisterKind Kind,
|
|
+ SMLoc S, SMLoc E) {
|
|
+ SparcOperand *Op = new SparcOperand(k_Register);
|
|
+ Op->Reg.RegNum = RegNum;
|
|
+ Op->Reg.Kind = Kind;
|
|
+ Op->StartLoc = S;
|
|
+ Op->EndLoc = E;
|
|
+ return Op;
|
|
+ }
|
|
+
|
|
+ static SparcOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
|
|
+ SparcOperand *Op = new SparcOperand(k_Immediate);
|
|
+ Op->Imm.Val = Val;
|
|
+ Op->StartLoc = S;
|
|
+ Op->EndLoc = E;
|
|
+ return Op;
|
|
+ }
|
|
+
|
|
+
|
|
+};
|
|
+
|
|
+} // end namespace
|
|
+
|
|
+bool SparcAsmParser::
|
|
+MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
|
|
+ SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
+ MCStreamer &Out, unsigned &ErrorInfo,
|
|
+ bool MatchingInlineAsm) {
|
|
+ MCInst Inst;
|
|
+ SmallVector<MCInst, 8> Instructions;
|
|
+ unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
|
|
+ MatchingInlineAsm);
|
|
+ switch (MatchResult) {
|
|
+ default:
|
|
+ break;
|
|
+
|
|
+ case Match_Success: {
|
|
+ Inst.setLoc(IDLoc);
|
|
+ Out.EmitInstruction(Inst);
|
|
+ return false;
|
|
+ }
|
|
+
|
|
+ case Match_MissingFeature:
|
|
+ return Error(IDLoc,
|
|
+ "instruction requires a CPU feature not currently enabled");
|
|
+
|
|
+ case Match_InvalidOperand: {
|
|
+ SMLoc ErrorLoc = IDLoc;
|
|
+ if (ErrorInfo != ~0U) {
|
|
+ if (ErrorInfo >= Operands.size())
|
|
+ return Error(IDLoc, "too few operands for instruction");
|
|
+
|
|
+ ErrorLoc = ((SparcOperand*) Operands[ErrorInfo])->getStartLoc();
|
|
+ if (ErrorLoc == SMLoc())
|
|
+ ErrorLoc = IDLoc;
|
|
+ }
|
|
+
|
|
+ return Error(ErrorLoc, "invalid operand for instruction");
|
|
+ }
|
|
+ case Match_MnemonicFail:
|
|
+ return Error(IDLoc, "invalid instruction");
|
|
+ }
|
|
+ return true;
|
|
+}
|
|
+
|
|
+bool SparcAsmParser::
|
|
+ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
|
|
+{
|
|
+ const AsmToken &Tok = Parser.getTok();
|
|
+ StartLoc = Tok.getLoc();
|
|
+ EndLoc = Tok.getEndLoc();
|
|
+ RegNo = 0;
|
|
+ if (getLexer().getKind() != AsmToken::Percent)
|
|
+ return false;
|
|
+ Parser.Lex();
|
|
+ if (matchRegisterName(Tok, RegNo, false, false)) {
|
|
+ Parser.Lex();
|
|
+ return false;
|
|
+ }
|
|
+
|
|
+ return Error(StartLoc, "invalid register name");
|
|
+}
|
|
+
|
|
+bool SparcAsmParser::
|
|
+ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
|
|
+ SMLoc NameLoc,
|
|
+ SmallVectorImpl<MCParsedAsmOperand*> &Operands)
|
|
+{
|
|
+ // Check if we have valid mnemonic.
|
|
+ if (!mnemonicIsValid(Name, 0)) {
|
|
+ Parser.eatToEndOfStatement();
|
|
+ return Error(NameLoc, "Unknown instruction");
|
|
+ }
|
|
+ // First operand in MCInst is instruction mnemonic.
|
|
+ Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
|
|
+
|
|
+ if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
+ // Read the first operand.
|
|
+ if (parseOperand(Operands, Name) != MatchOperand_Success) {
|
|
+ SMLoc Loc = getLexer().getLoc();
|
|
+ Parser.eatToEndOfStatement();
|
|
+ return Error(Loc, "unexpected token");
|
|
+ }
|
|
+
|
|
+ while (getLexer().is(AsmToken::Comma)) {
|
|
+ Parser.Lex(); // Eat the comma.
|
|
+ // Parse and remember the operand.
|
|
+ if (parseOperand(Operands, Name) != MatchOperand_Success) {
|
|
+ SMLoc Loc = getLexer().getLoc();
|
|
+ Parser.eatToEndOfStatement();
|
|
+ return Error(Loc, "unexpected token");
|
|
+ }
|
|
+ }
|
|
+ }
|
|
+ if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
+ SMLoc Loc = getLexer().getLoc();
|
|
+ Parser.eatToEndOfStatement();
|
|
+ return Error(Loc, "unexpected token");
|
|
+ }
|
|
+ Parser.Lex(); // Consume the EndOfStatement.
|
|
+ return false;
|
|
+}
|
|
+
|
|
+bool SparcAsmParser::
|
|
+ParseDirective(AsmToken DirectiveID)
|
|
+{
|
|
+ // Ignore all directives for now.
|
|
+ Parser.eatToEndOfStatement();
|
|
+ return false;
|
|
+}
|
|
+
|
|
+SparcAsmParser::OperandMatchResultTy SparcAsmParser::
|
|
+parseMEMOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
+ int ImmOffsetOrReg)
|
|
+{
|
|
+ // FIXME: Implement memory operand parsing here.
|
|
+ return MatchOperand_NoMatch;
|
|
+}
|
|
+
|
|
+SparcAsmParser::OperandMatchResultTy SparcAsmParser::
|
|
+parseMEMrrOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
|
|
+{
|
|
+ return parseMEMOperand(Operands, 2);
|
|
+}
|
|
+
|
|
+SparcAsmParser::OperandMatchResultTy SparcAsmParser::
|
|
+parseMEMriOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands)
|
|
+{
|
|
+ return parseMEMOperand(Operands, 1);
|
|
+}
|
|
+
|
|
+SparcAsmParser::OperandMatchResultTy SparcAsmParser::
|
|
+parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
+ StringRef Mnemonic)
|
|
+{
|
|
+ OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
|
|
+ if (ResTy == MatchOperand_Success)
|
|
+ return ResTy;
|
|
+ // If there wasn't a custom match, try the generic matcher below. Otherwise,
|
|
+ // there was a match, but an error occurred, in which case, just return that
|
|
+ // the operand parsing failed.
|
|
+ if (ResTy == MatchOperand_ParseFail)
|
|
+ return ResTy;
|
|
+
|
|
+ SMLoc S = Parser.getTok().getLoc();
|
|
+ SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
+ const MCExpr *EVal;
|
|
+ SparcOperand *Op;
|
|
+ switch (getLexer().getKind()) {
|
|
+ case AsmToken::Percent:
|
|
+ Parser.Lex(); // Eat the '%'.
|
|
+ unsigned RegNo;
|
|
+ if (matchRegisterName(Parser.getTok(), RegNo, false, false)) {
|
|
+ Parser.Lex(); // Eat the identifier token.
|
|
+ Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E);
|
|
+ break;
|
|
+ }
|
|
+ // FIXME: Handle modifiers like %hi, %lo etc.,
|
|
+ return MatchOperand_ParseFail;
|
|
+
|
|
+ case AsmToken::Minus:
|
|
+ case AsmToken::Integer:
|
|
+ if (getParser().parseExpression(EVal))
|
|
+ return MatchOperand_ParseFail;
|
|
+
|
|
+ Op = SparcOperand::CreateImm(EVal, S, E);
|
|
+ break;
|
|
+
|
|
+ case AsmToken::Identifier: {
|
|
+ StringRef Identifier;
|
|
+ if (getParser().parseIdentifier(Identifier))
|
|
+ return MatchOperand_ParseFail;
|
|
+ SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
+ MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
|
|
+
|
|
+ // Otherwise create a symbol reference.
|
|
+ const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
|
|
+ getContext());
|
|
+
|
|
+ Op = SparcOperand::CreateImm(Res, S, E);
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ case AsmToken::LBrac: // handle [
|
|
+ return parseMEMOperand(Operands, 0);
|
|
+
|
|
+ default:
|
|
+ return MatchOperand_ParseFail;
|
|
+ }
|
|
+ // Push the parsed operand into the list of operands
|
|
+ Operands.push_back(Op);
|
|
+ return MatchOperand_Success;
|
|
+}
|
|
+
|
|
+bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
|
|
+ unsigned &RegNo,
|
|
+ bool isDFP,
|
|
+ bool isQFP)
|
|
+{
|
|
+ int64_t intVal = 0;
|
|
+ RegNo = 0;
|
|
+ if (Tok.is(AsmToken::Identifier)) {
|
|
+ StringRef name = Tok.getString();
|
|
+
|
|
+ // %fp
|
|
+ if (name.equals("fp")) {
|
|
+ RegNo = Sparc::I6;
|
|
+ return true;
|
|
+ }
|
|
+ // %sp
|
|
+ if (name.equals("sp")) {
|
|
+ RegNo = Sparc::O6;
|
|
+ return true;
|
|
+ }
|
|
+
|
|
+ if (name.equals("y")) {
|
|
+ RegNo = Sparc::Y;
|
|
+ return true;
|
|
+ }
|
|
+
|
|
+ if (name.equals("icc")) {
|
|
+ RegNo = Sparc::ICC;
|
|
+ return true;
|
|
+ }
|
|
+
|
|
+ if (name.equals("xcc")) {
|
|
+ // FIXME:: check 64bit.
|
|
+ RegNo = Sparc::ICC;
|
|
+ return true;
|
|
+ }
|
|
+
|
|
+ // %fcc0 - %fcc3
|
|
+ if (name.substr(0, 3).equals_lower("fcc")
|
|
+ && !name.substr(3).getAsInteger(10, intVal)
|
|
+ && intVal < 4) {
|
|
+ // FIXME: check 64bit and handle %fcc1 - %fcc3
|
|
+ RegNo = Sparc::FCC;
|
|
+ return true;
|
|
+ }
|
|
+
|
|
+ // %g0 - %g7
|
|
+ if (name.substr(0, 1).equals_lower("g")
|
|
+ && !name.substr(1).getAsInteger(10, intVal)
|
|
+ && intVal < 8) {
|
|
+ RegNo = IntRegs[intVal];
|
|
+ return true;
|
|
+ }
|
|
+ // %o0 - %o7
|
|
+ if (name.substr(0, 1).equals_lower("o")
|
|
+ && !name.substr(1).getAsInteger(10, intVal)
|
|
+ && intVal < 8) {
|
|
+ RegNo = IntRegs[8 + intVal];
|
|
+ return true;
|
|
+ }
|
|
+ if (name.substr(0, 1).equals_lower("l")
|
|
+ && !name.substr(1).getAsInteger(10, intVal)
|
|
+ && intVal < 8) {
|
|
+ RegNo = IntRegs[16 + intVal];
|
|
+ return true;
|
|
+ }
|
|
+ if (name.substr(0, 1).equals_lower("i")
|
|
+ && !name.substr(1).getAsInteger(10, intVal)
|
|
+ && intVal < 8) {
|
|
+ RegNo = IntRegs[24 + intVal];
|
|
+ return true;
|
|
+ }
|
|
+ // %f0 - %f31
|
|
+ if (name.substr(0, 1).equals_lower("f")
|
|
+ && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
|
|
+ if (isDFP && (intVal%2 == 0)) {
|
|
+ RegNo = DoubleRegs[intVal/2];
|
|
+ } else if (isQFP && (intVal%4 == 0)) {
|
|
+ RegNo = QuadFPRegs[intVal/4];
|
|
+ } else {
|
|
+ RegNo = FloatRegs[intVal];
|
|
+ }
|
|
+ return true;
|
|
+ }
|
|
+ // %f32 - %f62
|
|
+ if (name.substr(0, 1).equals_lower("f")
|
|
+ && !name.substr(1, 2).getAsInteger(10, intVal)
|
|
+ && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
|
|
+ if (isDFP) {
|
|
+ RegNo = DoubleRegs[16 + intVal/2];
|
|
+ } else if (isQFP && (intVal % 4 == 0)) {
|
|
+ RegNo = QuadFPRegs[8 + intVal/4];
|
|
+ } else {
|
|
+ return false;
|
|
+ }
|
|
+ return true;
|
|
+ }
|
|
+
|
|
+ // %r0 - %r31
|
|
+ if (name.substr(0, 1).equals_lower("r")
|
|
+ && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
|
|
+ RegNo = IntRegs[intVal];
|
|
+ return true;
|
|
+ }
|
|
+ }
|
|
+ return false;
|
|
+}
|
|
+
|
|
+
|
|
+
|
|
+extern "C" void LLVMInitializeSparcAsmParser() {
|
|
+ RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
|
|
+ RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
|
|
+}
|
|
+
|
|
+#define GET_REGISTER_MATCHER
|
|
+#define GET_MATCHER_IMPLEMENTATION
|
|
+#include "SparcGenAsmMatcher.inc"
|
|
Index: lib/Target/Sparc/AsmParser/LLVMBuild.txt
|
|
===================================================================
|
|
--- lib/Target/Sparc/AsmParser/LLVMBuild.txt
|
|
+++ lib/Target/Sparc/AsmParser/LLVMBuild.txt
|
|
@@ -0,0 +1,23 @@
|
|
+;===- ./lib/Target/Sparc/AsmParser/LLVMBuild.txt ---------------*- Conf -*--===;
|
|
+;
|
|
+; The LLVM Compiler Infrastructure
|
|
+;
|
|
+; This file is distributed under the University of Illinois Open Source
|
|
+; License. See LICENSE.TXT for details.
|
|
+;
|
|
+;===------------------------------------------------------------------------===;
|
|
+;
|
|
+; This is an LLVMBuild description file for the components in this subdirectory.
|
|
+;
|
|
+; For more information on the LLVMBuild system, please see:
|
|
+;
|
|
+; http://llvm.org/docs/LLVMBuild.html
|
|
+;
|
|
+;===------------------------------------------------------------------------===;
|
|
+
|
|
+[component_0]
|
|
+type = Library
|
|
+name = SparcAsmParser
|
|
+parent = Sparc
|
|
+required_libraries = MC MCParser Support SparcDesc SparcInfo
|
|
+add_to_library_groups = Sparc
|
|
Index: lib/Target/Sparc/AsmParser/CMakeLists.txt
|
|
===================================================================
|
|
--- lib/Target/Sparc/AsmParser/CMakeLists.txt
|
|
+++ lib/Target/Sparc/AsmParser/CMakeLists.txt
|
|
@@ -0,0 +1,3 @@
|
|
+add_llvm_library(LLVMSparcAsmParser
|
|
+ SparcAsmParser.cpp
|
|
+ )
|
|
Index: lib/Target/Sparc/AsmParser/Makefile
|
|
===================================================================
|
|
--- lib/Target/Sparc/AsmParser/Makefile
|
|
+++ lib/Target/Sparc/AsmParser/Makefile
|
|
@@ -0,0 +1,15 @@
|
|
+##===- lib/Target/Sparc/AsmParser/Makefile ------------------*- Makefile-*-===##
|
|
+#
|
|
+# The LLVM Compiler Infrastructure
|
|
+#
|
|
+# This file is distributed under the University of Illinois Open Source
|
|
+# License. See LICENSE.TXT for details.
|
|
+#
|
|
+##===----------------------------------------------------------------------===##
|
|
+LEVEL = ../../../..
|
|
+LIBRARYNAME = LLVMSparcAsmParser
|
|
+
|
|
+# Hack: we need to include 'main' Sparc target directory to grab private headers
|
|
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
|
|
+
|
|
+include $(LEVEL)/Makefile.common
|
|
Index: lib/Target/Sparc/SparcInstr64Bit.td
|
|
===================================================================
|
|
--- lib/Target/Sparc/SparcInstr64Bit.td
|
|
+++ lib/Target/Sparc/SparcInstr64Bit.td
|
|
@@ -176,11 +176,11 @@ def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMP
|
|
def : Pat<(ctpop i64:$src), (POPCrr $src)>;
|
|
|
|
// "LEA" form of add
|
|
+let isCodeGenOnly = 1 in
|
|
def LEAX_ADDri : F3_2<2, 0b000000,
|
|
(outs I64Regs:$dst), (ins MEMri:$addr),
|
|
"add ${addr:arith}, $dst",
|
|
[(set iPTR:$dst, ADDRri:$addr)]>;
|
|
-
|
|
} // Predicates = [Is64Bit]
|
|
|
|
|