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freebsd-dev/contrib/llvm/patches/patch-r262261-llvm-r199977-sparc.diff
Dimitry Andric a1f8ad145e Add separate patch files for all the customizations we have currently 
applied to our copy of llvm/clang.  These can be applied in alphabetical
order to a pristine llvm/clang 3.4 release source tree, to result in the
same version used in FreeBSD.

This is intended to clearly document all the changes until now, which
mostly consist of cherry pickings from the respective upstream trunks,
plus a number of hand-written FreeBSD-specific ones.  Hopefully those
can eventually be cleaned up and sent upstream too.

MFC after:	1 week
X-MFC-With:	r263313
2014-03-18 22:07:45 +00:00

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Pull in r199977 from upstream llvm trunk (by Venkatraman Govindaraju):
[SparcV9] Add support for JIT in Sparc64.
With this change, all supported tests in test/ExecutionEngine pass in sparcv9.
Introduced here: http://svn.freebsd.org/changeset/base/262261
Index: lib/Target/Sparc/SparcJITInfo.cpp
===================================================================
--- lib/Target/Sparc/SparcJITInfo.cpp
+++ lib/Target/Sparc/SparcJITInfo.cpp
@@ -12,8 +12,9 @@
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "jit"
#include "SparcJITInfo.h"
+#include "Sparc.h"
#include "SparcRelocations.h"
-
+#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/JITCodeEmitter.h"
#include "llvm/Support/Memory.h"
@@ -35,18 +36,17 @@ extern "C" {
"SparcCompilationCallback:\n"
// Save current register window.
"\tsave %sp, -192, %sp\n"
- // stubaddr+4 is in %g1.
+ // stubaddr is in %g1.
"\tcall SparcCompilationCallbackC\n"
- "\t sub %g1, 4, %o0\n"
+ "\t mov %g1, %o0\n"
// restore original register window and
// copy %o0 to %g1
- "\t restore %o0, 0, %g1\n"
+ "\trestore %o0, 0, %g1\n"
// call the new stub
"\tjmp %g1\n"
"\t nop\n"
"\t.size SparcCompilationCallback, .-SparcCompilationCallback"
);
-
#else
void SparcCompilationCallback() {
llvm_unreachable(
@@ -55,33 +55,120 @@ extern "C" {
#endif
}
-#define HI(Val) (((unsigned)(Val)) >> 10)
-#define LO(Val) (((unsigned)(Val)) & 0x3FF)
#define SETHI_INST(imm, rd) (0x01000000 | ((rd) << 25) | ((imm) & 0x3FFFFF))
#define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \
| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
#define NOP_INST SETHI_INST(0, 0)
+#define OR_INST_I(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
+ | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
+#define OR_INST_R(rs1, rs2, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
+ | ((rs1) << 14) | (0 << 13) | ((rs2) & 0x1F))
+#define RDPC_INST(rd) (0x80000000 | ((rd) << 25) | (0x28 << 19) \
+ | (5 << 14))
+#define LDX_INST(rs1, imm, rd) (0xC0000000 | ((rd) << 25) | (0x0B << 19) \
+ | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
+#define SLLX_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x25 << 19) \
+ | ((rs1) << 14) | (3 << 12) | ((imm) & 0x3F))
+#define SUB_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x04 << 19) \
+ | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
+#define XOR_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x03 << 19) \
+ | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
+#define BA_INST(tgt) (0x10800000 | ((tgt) & 0x3FFFFF))
+// Emit instructions to jump to Addr and store the starting address of
+// the instructions emitted in the scratch register.
+static void emitInstrForIndirectJump(intptr_t Addr,
+ unsigned scratch,
+ SmallVectorImpl<uint32_t> &Insts) {
+
+ if (isInt<13>(Addr)) {
+ // Emit: jmpl %g0+Addr, <scratch>
+ // nop
+ Insts.push_back(JMP_INST(0, LO10(Addr), scratch));
+ Insts.push_back(NOP_INST);
+ return;
+ }
+
+ if (isUInt<32>(Addr)) {
+ // Emit: sethi %hi(Addr), scratch
+ // jmpl scratch+%lo(Addr), scratch
+ // sub scratch, 4, scratch
+ Insts.push_back(SETHI_INST(HI22(Addr), scratch));
+ Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch));
+ Insts.push_back(SUB_INST(scratch, 4, scratch));
+ return;
+ }
+
+ if (Addr < 0 && isInt<33>(Addr)) {
+ // Emit: sethi %hix(Addr), scratch)
+ // xor scratch, %lox(Addr), scratch
+ // jmpl scratch+0, scratch
+ // sub scratch, 8, scratch
+ Insts.push_back(SETHI_INST(HIX22(Addr), scratch));
+ Insts.push_back(XOR_INST(scratch, LOX10(Addr), scratch));
+ Insts.push_back(JMP_INST(scratch, 0, scratch));
+ Insts.push_back(SUB_INST(scratch, 8, scratch));
+ return;
+ }
+
+ // Emit: rd %pc, scratch
+ // ldx [scratch+16], scratch
+ // jmpl scratch+0, scratch
+ // sub scratch, 8, scratch
+ // <Addr: 8 byte>
+ Insts.push_back(RDPC_INST(scratch));
+ Insts.push_back(LDX_INST(scratch, 16, scratch));
+ Insts.push_back(JMP_INST(scratch, 0, scratch));
+ Insts.push_back(SUB_INST(scratch, 8, scratch));
+ Insts.push_back((uint32_t)(((int64_t)Addr) >> 32) & 0xffffffff);
+ Insts.push_back((uint32_t)(Addr & 0xffffffff));
+
+ // Instruction sequence without rdpc instruction
+ // 7 instruction and 2 scratch register
+ // Emit: sethi %hh(Addr), scratch
+ // or scratch, %hm(Addr), scratch
+ // sllx scratch, 32, scratch
+ // sethi %hi(Addr), scratch2
+ // or scratch, scratch2, scratch
+ // jmpl scratch+%lo(Addr), scratch
+ // sub scratch, 20, scratch
+ // Insts.push_back(SETHI_INST(HH22(Addr), scratch));
+ // Insts.push_back(OR_INST_I(scratch, HM10(Addr), scratch));
+ // Insts.push_back(SLLX_INST(scratch, 32, scratch));
+ // Insts.push_back(SETHI_INST(HI22(Addr), scratch2));
+ // Insts.push_back(OR_INST_R(scratch, scratch2, scratch));
+ // Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch));
+ // Insts.push_back(SUB_INST(scratch, 20, scratch));
+}
+
extern "C" void *SparcCompilationCallbackC(intptr_t StubAddr) {
// Get the address of the compiled code for this function.
intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr);
// Rewrite the function stub so that we don't end up here every time we
- // execute the call. We're replacing the first three instructions of the
- // stub with code that jumps to the compiled function:
- // sethi %hi(NewVal), %g1
- // jmp %g1+%lo(NewVal)
- // nop
+ // execute the call. We're replacing the stub instructions with code
+ // that jumps to the compiled function:
- *(intptr_t *)(StubAddr) = SETHI_INST(HI(NewVal), 1);
- *(intptr_t *)(StubAddr + 4) = JMP_INST(1, LO(NewVal), 0);
- *(intptr_t *)(StubAddr + 8) = NOP_INST;
+ SmallVector<uint32_t, 8> Insts;
+ intptr_t diff = (NewVal - StubAddr) >> 2;
+ if (isInt<22>(diff)) {
+ // Use branch instruction to jump
+ Insts.push_back(BA_INST(diff));
+ Insts.push_back(NOP_INST);
+ } else {
+ // Otherwise, use indirect jump to the compiled function
+ emitInstrForIndirectJump(NewVal, 1, Insts);
+ }
- sys::Memory::InvalidateInstructionCache((void*) StubAddr, 12);
+ for (unsigned i = 0, e = Insts.size(); i != e; ++i)
+ *(uint32_t *)(StubAddr + i*4) = Insts[i];
+
+ sys::Memory::InvalidateInstructionCache((void*) StubAddr, Insts.size() * 4);
return (void*)StubAddr;
}
+
void SparcJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
assert(0 && "FIXME: Implement SparcJITInfo::replaceMachineCodeForFunction");
}
@@ -88,10 +175,10 @@ void SparcJITInfo::replaceMachineCodeForFunction(v
TargetJITInfo::StubLayout SparcJITInfo::getStubLayout() {
- // The stub contains 3 4-byte instructions, aligned at 4 bytes. See
- // emitFunctionStub for details.
-
- StubLayout Result = { 3*4, 4 };
+ // The stub contains maximum of 4 4-byte instructions and 8 bytes for address,
+ // aligned at 32 bytes.
+ // See emitFunctionStub and emitInstrForIndirectJump for details.
+ StubLayout Result = { 4*4 + 8, 32 };
return Result;
}
@@ -98,32 +185,41 @@ TargetJITInfo::StubLayout SparcJITInfo::getStubLay
void *SparcJITInfo::emitFunctionStub(const Function *F, void *Fn,
JITCodeEmitter &JCE)
{
- JCE.emitAlignment(4);
+ JCE.emitAlignment(32);
void *Addr = (void*) (JCE.getCurrentPCValue());
- if (!sys::Memory::setRangeWritable(Addr, 12))
- llvm_unreachable("ERROR: Unable to mark stub writable.");
+ intptr_t CurrentAddr = (intptr_t)Addr;
intptr_t EmittedAddr;
- if (Fn != (void*)(intptr_t)SparcCompilationCallback)
+ SmallVector<uint32_t, 8> Insts;
+ if (Fn != (void*)(intptr_t)SparcCompilationCallback) {
EmittedAddr = (intptr_t)Fn;
- else
+ intptr_t diff = (EmittedAddr - CurrentAddr) >> 2;
+ if (isInt<22>(diff)) {
+ Insts.push_back(BA_INST(diff));
+ Insts.push_back(NOP_INST);
+ }
+ } else {
EmittedAddr = (intptr_t)SparcCompilationCallback;
+ }
- // sethi %hi(EmittedAddr), %g1
- // jmp %g1+%lo(EmittedAddr), %g1
- // nop
+ if (Insts.size() == 0)
+ emitInstrForIndirectJump(EmittedAddr, 1, Insts);
- JCE.emitWordBE(SETHI_INST(HI(EmittedAddr), 1));
- JCE.emitWordBE(JMP_INST(1, LO(EmittedAddr), 1));
- JCE.emitWordBE(NOP_INST);
- sys::Memory::InvalidateInstructionCache(Addr, 12);
- if (!sys::Memory::setRangeExecutable(Addr, 12))
+ if (!sys::Memory::setRangeWritable(Addr, 4 * Insts.size()))
+ llvm_unreachable("ERROR: Unable to mark stub writable.");
+
+ for (unsigned i = 0, e = Insts.size(); i != e; ++i)
+ JCE.emitWordBE(Insts[i]);
+
+ sys::Memory::InvalidateInstructionCache(Addr, 4 * Insts.size());
+ if (!sys::Memory::setRangeExecutable(Addr, 4 * Insts.size()))
llvm_unreachable("ERROR: Unable to mark stub executable.");
return Addr;
}
+
TargetJITInfo::LazyResolverFn
SparcJITInfo::getLazyResolverFunction(JITCompilerFn F) {
JITCompilerFunction = F;
@@ -159,6 +255,27 @@ void SparcJITInfo::relocate(void *Function, Machin
case SP::reloc_sparc_pc19:
ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x7ffff;
break;
+
+ case SP::reloc_sparc_h44:
+ ResultPtr = (ResultPtr >> 22) & 0x3fffff;
+ break;
+
+ case SP::reloc_sparc_m44:
+ ResultPtr = (ResultPtr >> 12) & 0x3ff;
+ break;
+
+ case SP::reloc_sparc_l44:
+ ResultPtr = (ResultPtr & 0xfff);
+ break;
+
+ case SP::reloc_sparc_hh:
+ ResultPtr = (((int64_t)ResultPtr) >> 42) & 0x3fffff;
+ break;
+
+ case SP::reloc_sparc_hm:
+ ResultPtr = (((int64_t)ResultPtr) >> 32) & 0x3ff;
+ break;
+
}
*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
}
Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
===================================================================
--- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
+++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
@@ -68,9 +68,13 @@ static MCCodeGenInfo *createSparcMCCodeGenInfo(Str
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
- // The default 32-bit code model is abs32/pic32.
- if (CM == CodeModel::Default)
- CM = RM == Reloc::PIC_ ? CodeModel::Medium : CodeModel::Small;
+ // The default 32-bit code model is abs32/pic32 and the default 32-bit
+ // code model for JIT is abs32.
+ switch (CM) {
+ default: break;
+ case CodeModel::Default:
+ case CodeModel::JITDefault: CM = CodeModel::Small; break;
+ }
X->InitMCCodeGenInfo(RM, CM, OL);
return X;
@@ -81,9 +85,17 @@ static MCCodeGenInfo *createSparcV9MCCodeGenInfo(S
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
- // The default 64-bit code model is abs44/pic32.
- if (CM == CodeModel::Default)
- CM = CodeModel::Medium;
+ // The default 64-bit code model is abs44/pic32 and the default 64-bit
+ // code model for JIT is abs64.
+ switch (CM) {
+ default: break;
+ case CodeModel::Default:
+ CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
+ break;
+ case CodeModel::JITDefault:
+ CM = CodeModel::Large;
+ break;
+ }
X->InitMCCodeGenInfo(RM, CM, OL);
return X;
Index: lib/Target/Sparc/SparcISelLowering.cpp
===================================================================
--- lib/Target/Sparc/SparcISelLowering.cpp
+++ lib/Target/Sparc/SparcISelLowering.cpp
@@ -1810,7 +1810,6 @@ SDValue SparcTargetLowering::makeAddress(SDValue O
switch(getTargetMachine().getCodeModel()) {
default:
llvm_unreachable("Unsupported absolute code model");
- case CodeModel::JITDefault:
case CodeModel::Small:
// abs32.
return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
Index: lib/Target/Sparc/SparcCodeEmitter.cpp
===================================================================
--- lib/Target/Sparc/SparcCodeEmitter.cpp
+++ lib/Target/Sparc/SparcCodeEmitter.cpp
@@ -207,11 +207,11 @@ unsigned SparcCodeEmitter::getRelocation(const Mac
case SPII::MO_NO_FLAG: break;
case SPII::MO_LO: return SP::reloc_sparc_lo;
case SPII::MO_HI: return SP::reloc_sparc_hi;
- case SPII::MO_H44:
- case SPII::MO_M44:
- case SPII::MO_L44:
- case SPII::MO_HH:
- case SPII::MO_HM: assert(0 && "FIXME: Implement Medium/Large code model.");
+ case SPII::MO_H44: return SP::reloc_sparc_h44;
+ case SPII::MO_M44: return SP::reloc_sparc_m44;
+ case SPII::MO_L44: return SP::reloc_sparc_l44;
+ case SPII::MO_HH: return SP::reloc_sparc_hh;
+ case SPII::MO_HM: return SP::reloc_sparc_hm;
}
unsigned Opc = MI.getOpcode();
Index: lib/Target/Sparc/SparcRelocations.h
===================================================================
--- lib/Target/Sparc/SparcRelocations.h
+++ lib/Target/Sparc/SparcRelocations.h
@@ -33,7 +33,22 @@ namespace llvm {
reloc_sparc_pc22 = 4,
// reloc_sparc_pc22 - pc rel. 19 bits for branch with icc/xcc
- reloc_sparc_pc19 = 5
+ reloc_sparc_pc19 = 5,
+
+ // reloc_sparc_h44 - 43-22 bits
+ reloc_sparc_h44 = 6,
+
+ // reloc_sparc_m44 - 21-12 bits
+ reloc_sparc_m44 = 7,
+
+ // reloc_sparc_l44 - lower 12 bits
+ reloc_sparc_l44 = 8,
+
+ // reloc_sparc_hh - 63-42 bits
+ reloc_sparc_hh = 9,
+
+ // reloc_sparc_hm - 41-32 bits
+ reloc_sparc_hm = 10
};
}
}
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