a1f8ad145e
applied to our copy of llvm/clang. These can be applied in alphabetical order to a pristine llvm/clang 3.4 release source tree, to result in the same version used in FreeBSD. This is intended to clearly document all the changes until now, which mostly consist of cherry pickings from the respective upstream trunks, plus a number of hand-written FreeBSD-specific ones. Hopefully those can eventually be cleaned up and sent upstream too. MFC after: 1 week X-MFC-With: r263313
92 lines
3.5 KiB
Diff
92 lines
3.5 KiB
Diff
Pull in r200453 from upstream llvm trunk (by Jakob Stoklund Olesen):
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Implement SPARCv9 atomic_swap_64 with a pseudo.
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The SWAP instruction only exists in a 32-bit variant, but the 64-bit
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atomic swap can be implemented in terms of CASX, like the other atomic
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rmw primitives.
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Introduced here: http://svn.freebsd.org/changeset/base/262264
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Index: lib/Target/Sparc/SparcInstr64Bit.td
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===================================================================
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--- lib/Target/Sparc/SparcInstr64Bit.td
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+++ lib/Target/Sparc/SparcInstr64Bit.td
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@@ -463,6 +463,14 @@ defm ATOMIC_LOAD_MAX : AtomicRMW<atomic_load_max_
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defm ATOMIC_LOAD_UMIN : AtomicRMW<atomic_load_umin_32, atomic_load_umin_64>;
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defm ATOMIC_LOAD_UMAX : AtomicRMW<atomic_load_umax_32, atomic_load_umax_64>;
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+// There is no 64-bit variant of SWAP, so use a pseudo.
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+let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1,
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+ Defs = [ICC], Predicates = [Is64Bit] in
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+def ATOMIC_SWAP_64 : Pseudo<(outs I64Regs:$rd),
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+ (ins ptr_rc:$addr, I64Regs:$rs2), "",
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+ [(set i64:$rd,
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+ (atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
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+
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// Global addresses, constant pool entries
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let Predicates = [Is64Bit] in {
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Index: lib/Target/Sparc/SparcISelLowering.cpp
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===================================================================
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--- lib/Target/Sparc/SparcISelLowering.cpp
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+++ lib/Target/Sparc/SparcISelLowering.cpp
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@@ -1498,7 +1498,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMac
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
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- setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
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+ setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
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setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
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}
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@@ -2885,6 +2885,9 @@ SparcTargetLowering::EmitInstrWithCustomInserter(M
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case SP::ATOMIC_LOAD_NAND_64:
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return expandAtomicRMW(MI, BB, SP::ANDXrr);
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+ case SP::ATOMIC_SWAP_64:
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+ return expandAtomicRMW(MI, BB, 0);
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+
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case SP::ATOMIC_LOAD_MAX_32:
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return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
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case SP::ATOMIC_LOAD_MAX_64:
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@@ -3023,7 +3026,8 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr
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// Build the loop block.
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unsigned ValReg = MRI.createVirtualRegister(ValueRC);
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- unsigned UpdReg = MRI.createVirtualRegister(ValueRC);
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+ // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP).
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+ unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg);
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BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
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.addReg(Val0Reg).addMBB(MBB)
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@@ -3035,7 +3039,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr
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BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
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BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
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.addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
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- } else {
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+ } else if (Opcode) {
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BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
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.addReg(ValReg).addReg(Rs2Reg);
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}
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Index: test/CodeGen/SPARC/atomics.ll
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===================================================================
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--- test/CodeGen/SPARC/atomics.ll
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+++ test/CodeGen/SPARC/atomics.ll
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@@ -62,6 +62,15 @@ entry:
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ret i32 %b
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}
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+; CHECK-LABEL: test_swap_i64
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+; CHECK: casx [%o1],
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+
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+define i64 @test_swap_i64(i64 %a, i64* %ptr) {
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+entry:
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+ %b = atomicrmw xchg i64* %ptr, i64 42 monotonic
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+ ret i64 %b
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+}
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+
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; CHECK-LABEL: test_load_add_32
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; CHECK: membar
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; CHECK: add [[V:%[gilo][0-7]]], %o1, [[U:%[gilo][0-7]]]
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