7c12b677f5
These are older MIPS4kc parts from Atheros. They typically ran at sub-200MHz and have 11bg, 11a, or 11abg wifi MAC/PHYs integrated. This port is the initial non-wifi pieces required to bring up the chip. I'll commit the redboot and other pieces later, and then hopefully(!) wifi support will follow. Submitted by: Mori Hiroki <yamori813@yahoo.co.jp> Differential Revision: https://reviews.freebsd.org/D7237
76 lines
2.5 KiB
C
76 lines
2.5 KiB
C
/*-
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* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* Copyright (c) 2009, Luiz Otavio O Souza.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __AR5315_GPIOVAR_H__
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#define __AR5315_GPIOVAR_H__
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#include <sys/timepps.h>
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#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->gpio_mtx)
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#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->gpio_mtx)
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#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->gpio_mtx, MA_OWNED)
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/*
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* register space access macros
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*/
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#define GPIO_WRITE(sc, reg, val) do { \
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bus_write_4(sc->gpio_mem_res, (reg), (val)); \
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} while (0)
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#define GPIO_READ(sc, reg) bus_read_4(sc->gpio_mem_res, (reg))
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#define GPIO_SET_BITS(sc, reg, bits) \
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GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) | (bits))
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#define GPIO_CLEAR_BITS(sc, reg, bits) \
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GPIO_WRITE(sc, reg, GPIO_READ(sc, (reg)) & ~(bits))
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#define AR5315_GPIO_PINS 23
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#define AR5312_GPIO_PINS 8
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struct ar5315_gpio_softc {
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device_t dev;
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device_t busdev;
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struct mtx gpio_mtx;
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struct resource *gpio_mem_res;
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int gpio_mem_rid;
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struct resource *gpio_irq_res;
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int gpio_irq_rid;
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void *gpio_ih;
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int gpio_npins;
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struct gpio_pin *gpio_pins;
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int gpio_ppspin;
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struct pps_state gpio_pps;
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uint32_t gpio_ppsenable;
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};
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#endif /* __AR5315_GPIOVAR_H__ */
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