9efd0ba788
Add support for pci deviceID 0x8070 for QLE41xxx product line which supports 10GbE/25GbE/40GbE MFC after:5 days
383 lines
12 KiB
C
383 lines
12 KiB
C
/*
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* Copyright (c) 2017-2018 Cavium, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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/****************************************************************************
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*
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* Name: mcp_private.h
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*
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* Description: MCP private data. Located in HSI only to provide debug access
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* for diag.
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*
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****************************************************************************/
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#ifndef MCP_PRIVATE_H
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#define MCP_PRIVATE_H
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#if (!defined MFW_SIM) && (!defined RECOVERY)
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#include "eth.h"
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#include "pmm.h"
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#include "ah_eth.h"
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#endif
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#include "mcp_public.h"
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typedef enum active_mf_mode {
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MF_MODE_SF = 0,
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MF_MODE_MF_ALLOWED,
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MF_MODE_MF_SWITCH_INDEPENDENT,
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MF_MODE_NIV
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} active_mf_mode_t;
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enum ov_current_cfg {
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CURR_CFG_NONE = 0,
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CURR_CFG_OS,
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CURR_CFG_VENDOR_SPEC,
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CURR_CFG_OTHER,
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CURR_CFG_VC_CLP,
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CURR_CFG_CNU,
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CURR_CFG_DCI,
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CURR_CFG_HII,
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};
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struct dci_info_global {
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enum ov_current_cfg current_cfg;
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u8 pci_bus_num;
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u8 boot_progress;
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};
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/* Resource allocation information of one resource */
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struct resource_info_private {
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u16 size; /* number of allocated resources */
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u16 offset; /* Offset of the 1st resource */
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u8 flags;
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};
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/* Cache for resource allocation of one PF */
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struct res_alloc_cache {
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u8 pf_num;
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struct resource_info_private res[RESOURCE_MAX_NUM];
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};
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struct pf_sb_t {
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u8 sb_for_pf_size;
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u8 sb_for_pf_offset;
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u8 sb_for_vf_size;
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u8 sb_for_vf_offset;
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};
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/**************************************/
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/* */
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/* P R I V A T E G L O B A L */
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/* */
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/**************************************/
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struct private_global {
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active_mf_mode_t mf_mode; /* TBD - require initialization */
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u32 exp_rom_nvm_addr;
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/* The pmm_config structure holds all active phy/link configuration */
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#ifndef RECOVERY
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#ifdef b900
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struct pmm_config eth_cfg;
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#else
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struct ah_eth eth_cfg;
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#endif
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#endif
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u32 lldp_counter;
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u32 avs_init_timestamp;
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u32 seconds_since_mcp_reset;
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u32 last_malloc_dir_used_timestamp;
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#define MAX_USED_DIR_ALLOWED_TIME (3) /* Seconds */
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u32 drv_nvm_state;
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/* Per PF bitmask */
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#define DRV_NVM_STATE_IN_PROGRESS_MASK (0x0000ffff)
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#define DRV_NVM_STATE_IN_PROGRESS_OFFSET (0)
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u32 storm_fw_ver;
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/* OneView data*/
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struct dci_info_global dci_global;
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/* Resource allocation cached data */
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struct res_alloc_cache res_alloc;
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#define G_RES_ALLOC_P (&g_spad.private_data.global.res_alloc)
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u32 resource_max_values[RESOURCE_MAX_NUM];
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};
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/**************************************/
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/* */
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/* P R I V A T E P A T H */
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/* */
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/**************************************/
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struct private_path {
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u32 recovery_countdown; /* Counting down 2 seconds, using TMR3 */
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#define RECOVERY_MAX_COUNTDOWN_SECONDS 2
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u32 drv_load_vars; /* When the seconds_since_mcp_reset gets here */
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#define DRV_LOAD_TIMEOUT_MASK 0x0000ffff
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#define DRV_LOAD_TIMEOUT_OFFSET 0
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#define DRV_LOAD_NEED_FORCE_MASK 0xffff0000
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#define DRV_LOAD_NEED_FORCE_OFFSET 16
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struct load_rsp_stc drv_load_params;
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};
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/**************************************/
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/* */
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/* P R I V A T E P O R T */
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/* */
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/**************************************/
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struct drv_port_info_t {
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u32_t port_state;
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#define DRV_STATE_LINK_LOCK_FLAG 0x00000001
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#define DRV_WAIT_DBG_PRN 0x00000002
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/* There are maximum 8 PFs per port */
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#define DRV_STATE_LOADED_MASK 0x0000ff00
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#define DRV_STATE_LOADED_OFFSET 8
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#define DRV_STATE_PF_TRANSITION_MASK 0x00ff0000
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#define DRV_STATE_PF_TRANSITION_OFFSET 16
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#define DRV_STATE_PF_PHY_INIT_MASK 0xff000000
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#define DRV_STATE_PF_PHY_INIT_OFFSET 24
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};
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typedef enum _lldp_subscriber_e {
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LLDP_SUBSCRIBER_MANDATORY = 0,
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LLDP_SUBSCRIBER_DCBX_IEEE,
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LLDP_SUBSCRIBER_DCBX_CEE,
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LLDP_SUBSCRIBER_EEE,
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LLDP_SUBSCRIBER_DCI,
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MAX_SUBSCRIBERS
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} lldp_subscriber_e;
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typedef struct {
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u16 valid;
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u16 type_len;
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#define LLDP_LEN_MASK (0x01ff)
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#define LLDP_LEN_OFFSET (0)
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#define LLDP_TYPE_MASK (0xfe00)
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#define LLDP_TYPE_OFFSET (9)
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u8 *value_p;
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} tlv_s;
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typedef u16(*lldp_prepare_tlv_func)(u8 port, lldp_agent_e lldp_agent, u8 *buffer);
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typedef struct {
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u16 valid;
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lldp_prepare_tlv_func func;
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} subscriber_callback_send_s;
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typedef u8(*lldp_process_func)(u8 port, u8 num, u8 **tlvs);
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#define MAX_NUM_SUBTYPES 4
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typedef struct {
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u8 valid;
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u8 oui[3];
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u8 subtype_list[MAX_NUM_SUBTYPES];
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u8 num_subtypes;
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lldp_process_func func;
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} subscriber_callback_receive_s;
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#define MAX_ETH_HEADER 14 /* TODO: to be extended per requirements */
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#define MAX_PACKET_SIZE (1516) /* So it can be devided by 4 */
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#define LLDP_CHASSIS_ID_TLV_LEN 7
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#define LLDP_PORT_ID_TLV_LEN 7
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#define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/
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typedef struct {
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u16 len;
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u8 header[MAX_ETH_HEADER];
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} lldp_eth_header_s;
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typedef struct {
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struct lldp_config_params_s lldp_config_params;
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u16 lldp_ttl;
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u8 lldp_cur_credit;
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subscriber_callback_send_s subscriber_callback_send[MAX_SUBSCRIBERS];
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lldp_eth_header_s lldp_eth_header;
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u32 lldp_time_to_send;
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u32 lldp_ttl_expired;
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u32 lldp_sent;
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u8 first_lldp;
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subscriber_callback_receive_s subscriber_callback_receive[MAX_SUBSCRIBERS];
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} lldp_params_s;
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#define MAX_TLVS 20
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typedef struct {
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u8 current_received_tlv_index;
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u8 *received_tlvs[MAX_TLVS];
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} lldp_receive_data_s;
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#define MAX_REGISTERED_TLVS 6
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typedef struct {
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u32 config; /* Uses same defines as local config plus some more below*/
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#define DCBX_MODE_MASK 0x00000010
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#define DCBX_MODE_OFFSET 4
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#define DCBX_MODE_DRIVER 0
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#define DCBX_MODE_DEFAULT 1
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#define DCBX_CHANGED_MASK 0x00000f00
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#define DCBX_CHANGED_OFFSET 8
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#define DCBX_CONTROL_CHANGED_MASK 0x00000100
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#define DCBX_CONTROL_CHANGED_OFFSET 8
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#define DCBX_PFC_CHANGED_MASK 0x00000200
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#define DCBX_PFC_CHANGED_OFFSET 9
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#define DCBX_ETS_CHANGED_MASK 0x00000400
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#define DCBX_ETS_CHANGED_OFFSET 10
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#define DCBX_APP_CHANGED_MASK 0x00000800
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#define DCBX_APP_CHANGED_OFFSET 11
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u32 seq_no;
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u32 ack_no;
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u32 received_seq_no;
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u8 tc_map[8];
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u8 num_used_tcs;
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} dcbx_state_s;
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#ifdef CONFIG_HP_DCI_SUPPORT
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struct dci_info_port {
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u32 config;
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#define DCI_PORT_CFG_ENABLE_OFFSET (0)
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#define DCI_PORT_CFG_ENABLE_MASK (1 << DCI_PORT_CFG_ENABLE_OFFSET)
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#define DCI_PORT_CFG_ENABLE_DIAG_OFFSET (1)
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#define DCI_PORT_CFG_ENABLE_DIAG_MASK (1 << DCI_PORT_CFG_ENABLE_DIAG_OFFSET)
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#define DCI_PORT_CFG_DIAG_L_LOOP_OFFSET (2)
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#define DCI_PORT_CFG_DIAG_L_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_L_LOOP_OFFSET)
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#define DCI_PORT_CFG_DIAG_R_LOOP_OFFSET (3)
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#define DCI_PORT_CFG_DIAG_R_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_R_LOOP_OFFSET)
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};
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#endif
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struct private_port {
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struct drv_port_info_t port_info;
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active_mf_mode_t mf_mode;
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u32 prev_link_change_count;
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/* LLDP structures */
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lldp_params_s lldp_params[LLDP_MAX_LLDP_AGENTS];
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lldp_receive_data_s lldp_receive_data[MAX_SUBSCRIBERS];
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/* DCBX */
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dcbx_state_s dcbx_state;
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u32 net_buffer[MAX_PACKET_SIZE / 4]; /* Buffer to send any packet to network */
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/* time stamp of the end of NIG drain time for the TX drain */
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u32 nig_drain_end_ts;
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/* time stamp of the end of NIG drain time for the TC pause drain, this timer is used togther for all TC */
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u32 nig_drain_tc_end_ts;
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u32 tc_drain_en_bitmap;
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u32 recv_lldp_tlvs[LLDP_MAX_LLDP_AGENTS][MAX_TLV_BUFFER];
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tlv_s lldp_core_tlv_desc[LLDP_MAX_LLDP_AGENTS][MAX_REGISTERED_TLVS];
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u8 current_core_tlv_num[LLDP_MAX_LLDP_AGENTS];
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struct mcp_mac lldp_mac;
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#ifdef CONFIG_HP_DCI_SUPPORT
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struct dci_info_port dci_port;
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#endif
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u32 temperature;
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};
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/**************************************/
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/* */
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/* P R I V A T E F U N C */
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/* */
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/**************************************/
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struct drv_func_info_t {
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u32_t func_state;
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#define DRV_STATE_UNKNOWN 0x00000000
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#define DRV_STATE_UNLOADED 0x00000001
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#define DRV_STATE_D3 0x00000004
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#define DRV_STATE_PRESENT_FLAG 0x00000100
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#define DRV_STATE_RUNNING (0x00000002 | DRV_STATE_PRESENT_FLAG)
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#define DRV_STATE_NOT_RESPONDING 0x00000003 /* Will result with non-zero value when compared with DRV_STATE_RUNNING or with DRV_STATE_UNLOADED */
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#define DRV_STATE_BACK_AFTER_TO (DRV_STATE_NOT_RESPONDING | DRV_STATE_PRESENT_FLAG)
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#define DRV_STATE_DIAG (0x00000010 | DRV_STATE_PRESENT_FLAG)
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#define DRV_STATE_TRANSITION_FLAG 0x00001000
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#define DRV_STATE_LOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG)
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#define DRV_STATE_UNLOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG | DRV_STATE_UNLOADED)
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u32_t driver_last_activity;
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u32_t wol_mac_addr[2];
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u32_t drv_feature_support; /* See DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_* */
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u8_t unload_wol_param; /* See drv_mb_param */
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u8_t eswitch_mode;
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};
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struct dci_info_func {
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u8 config;
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#define DCI_FUNC_CFG_FNIC_ENABLE_OFFSET (0)
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#define DCI_FUNC_CFG_FNIC_ENABLE_MASK (1 << DCI_FUNC_CFG_FNIC_ENABLE_OFFSET)
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#define DCI_FUNC_CFG_OS_MTU_OVERRIDE_OFFSET (1)
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#define DCI_FUNC_CFG_OS_MTU_OVERRIDE_MASK (1 << DCI_FUNC_CFG_OS_MTU_OVERRIDE_OFFSET)
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#define DCI_FUNC_CFG_DIAG_WOL_ENABLE_OFFSET (2)
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#define DCI_FUNC_CFG_DIAG_WOL_ENABLE_MASK (1 << DCI_FUNC_CFG_DIAG_WOL_ENABLE_OFFSET)
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u8 drv_state;
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u16 fcoe_cvid;
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u8 fcoe_fabric_name[8];
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};
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struct private_func {
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struct drv_func_info_t func_info;
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u32 init_hw_page;
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u32 num_of_msix;
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struct pf_sb_t sb;
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struct dci_info_func dci_func;
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};
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/**************************************/
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/* */
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/* P R I V A T E D A T A */
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/* */
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/**************************************/
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struct mcp_private_data {
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/* Basically no need for section offsets here, since this is private data.
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* TBD - should consider adding section offsets if we want diag to parse this correctly !!
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*/
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struct private_global global;
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struct private_path path[MCP_GLOB_PATH_MAX];
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struct private_port port[MCP_GLOB_PORT_MAX];
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struct private_func func[MCP_GLOB_FUNC_MAX];
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};
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#endif /* MCP_PRIVATE_H */
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