8a03f98a8b
- Added bhnd(4) bus APIs for per-core ioctl/iost register access. - Updated reset/suspend bhnd(4) APIs for compatibility with ioctl/iost changes. - Implemented core reset/suspend support for both bcma(4) and siba(4). - Implemented explicit release of all outstanding PMU requests at the bus level when putting a core into reset. Approved by: adrian (mentor, implicit) Differential Revision: https://reviews.freebsd.org/D8009
268 lines
11 KiB
C
268 lines
11 KiB
C
/*-
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* Copyright (c) 2015 Landon Fuller <landon@landonf.org>
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* Copyright (c) 2010 Broadcom Corporation
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*
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* This file was derived from the sbconfig.h header distributed with
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* Broadcom's initial brcm80211 Linux driver release, as
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* contributed to the Linux staging repository.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef _BHND_SIBA_SIBAREG_
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#define _BHND_SIBA_SIBAREG_
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#include <dev/bhnd/bhndreg.h>
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/*
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* Broadcom SIBA Configuration Space Registers.
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*
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* Backplane configuration registers common to siba(4) core register
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* blocks.
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*/
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/**
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* Extract a config attribute by applying _MASK and _SHIFT defines.
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*
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* @param _reg The register value containing the desired attribute
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* @param _attr The BCMA EROM attribute name (e.g. ENTRY_ISVALID), to be
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* concatenated with the `SB` prefix and `_MASK`/`_SHIFT` suffixes.
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*/
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#define SIBA_REG_GET(_entry, _attr) \
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((_entry & SIBA_ ## _attr ## _MASK) \
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>> SIBA_ ## _attr ## _SHIFT)
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#define SIBA_ENUM_ADDR BHND_DEFAULT_CHIPC_ADDR /**< enumeration space */
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#define SIBA_ENUM_SIZE 0x00100000 /**< size of the enumeration space */
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#define SIBA_CORE_SIZE BHND_DEFAULT_CORE_SIZE /**< per-core register block size */
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#define SIBA_CORE_NUM_INTR 1 /**< number of per-core interrupt lines */
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#define SIBA_MAX_CORES \
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(SIBA_ENUM_SIZE/SIBA_CORE_SIZE) /**< Maximum number of cores */
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/** Evaluates to the bus address offset of the @p idx core register block */
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#define SIBA_CORE_OFFSET(idx) ((idx) * SIBA_CORE_SIZE)
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/** Evaluates to the bus address of the @p idx core register block */
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#define SIBA_CORE_ADDR(idx) (SIBA_ENUM_ADDR + SIBA_CORE_OFFSET(idx))
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/*
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* Sonics configuration registers are mapped to each core's enumeration
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* space, at the end of the 4kb device register block, in reverse
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* order:
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*
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* [0x0000-0x0dff] core registers
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* [0x0e00-0x0eff] SIBA_R1 registers (sonics >= 2.3)
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* [0x0f00-0x0fff] SIBA_R0 registers
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*/
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#define SIBA_CFG0_OFFSET 0xf00 /**< first configuration block */
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#define SIBA_CFG1_OFFSET 0xe00 /**< second configuration block (sonics >= 2.3) */
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#define SIBA_CFG_SIZE 0x100 /**< cfg register block size */
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/* Return the SIBA_CORE_ADDR-relative offset for a SIBA_CFG* register. */
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#define SB0_REG_ABS(off) ((off) + SIBA_CFG0_OFFSET)
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#define SB1_REG_ABS(off) ((off) + SIBA_CFG1_OFFSET)
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/* SIBA_CFG0 registers */
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#define SIBA_CFG0_IPSFLAG 0x08 /**< initiator port ocp slave flag */
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#define SIBA_CFG0_TPSFLAG 0x18 /**< target port ocp slave flag */
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#define SIBA_CFG0_TMERRLOGA 0x48 /**< sonics >= 2.3 */
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#define SIBA_CFG0_TMERRLOG 0x50 /**< sonics >= 2.3 */
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#define SIBA_CFG0_ADMATCH3 0x60 /**< address match3 */
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#define SIBA_CFG0_ADMATCH2 0x68 /**< address match2 */
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#define SIBA_CFG0_ADMATCH1 0x70 /**< address match1 */
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#define SIBA_CFG0_IMSTATE 0x90 /**< initiator agent state */
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#define SIBA_CFG0_INTVEC 0x94 /**< interrupt mask */
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#define SIBA_CFG0_TMSTATELOW 0x98 /**< target state */
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#define SIBA_CFG0_TMSTATEHIGH 0x9c /**< target state */
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#define SIBA_CFG0_BWA0 0xa0 /**< bandwidth allocation table0 */
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#define SIBA_CFG0_IMCONFIGLOW 0xa8 /**< initiator configuration */
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#define SIBA_CFG0_IMCONFIGHIGH 0xac /**< initiator configuration */
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#define SIBA_CFG0_ADMATCH0 0xb0 /**< address match0 */
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#define SIBA_CFG0_TMCONFIGLOW 0xb8 /**< target configuration */
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#define SIBA_CFG0_TMCONFIGHIGH 0xbc /**< target configuration */
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#define SIBA_CFG0_BCONFIG 0xc0 /**< broadcast configuration */
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#define SIBA_CFG0_BSTATE 0xc8 /**< broadcast state */
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#define SIBA_CFG0_ACTCNFG 0xd8 /**< activate configuration */
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#define SIBA_CFG0_FLAGST 0xe8 /**< current sbflags */
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#define SIBA_CFG0_IDLOW 0xf8 /**< identification */
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#define SIBA_CFG0_IDHIGH 0xfc /**< identification */
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/* SIBA_CFG1 registers (sonics >= 2.3) */
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#define SIBA_CFG1_IMERRLOGA 0xa8 /**< (sonics >= 2.3) */
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#define SIBA_CFG1_IMERRLOG 0xb0 /**< sbtmerrlog (sonics >= 2.3) */
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#define SIBA_CFG1_TMPORTCONNID0 0xd8 /**< sonics >= 2.3 */
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#define SIBA_CFG1_TMPORTLOCK0 0xf8 /**< sonics >= 2.3 */
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/* sbipsflag */
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#define SIBA_IPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
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#define SIBA_IPS_INT1_SHIFT 0
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#define SIBA_IPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
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#define SIBA_IPS_INT2_SHIFT 8
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#define SIBA_IPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
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#define SIBA_IPS_INT3_SHIFT 16
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#define SIBA_IPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
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#define SIBA_IPS_INT4_SHIFT 24
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/* sbtpsflag */
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#define SIBA_TPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
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#define SIBA_TPS_NUM0_SHIFT 0
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#define SIBA_TPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
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/* sbtmerrlog */
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#define SIBA_TMEL_CM 0x00000007 /* command */
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#define SIBA_TMEL_CI 0x0000ff00 /* connection id */
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#define SIBA_TMEL_EC 0x0f000000 /* error code */
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#define SIBA_TMEL_ME 0x80000000 /* multiple error */
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/* sbimstate */
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#define SIBA_IM_PC 0xf /* pipecount */
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#define SIBA_IM_AP_MASK 0x30 /* arbitration policy */
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#define SIBA_IM_AP_BOTH 0x00 /* use both timeslaces and token */
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#define SIBA_IM_AP_TS 0x10 /* use timesliaces only */
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#define SIBA_IM_AP_TK 0x20 /* use token only */
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#define SIBA_IM_AP_RSV 0x30 /* reserved */
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#define SIBA_IM_IBE 0x20000 /* inbanderror */
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#define SIBA_IM_TO 0x40000 /* timeout */
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#define SIBA_IM_BY 0x01800000 /* busy (sonics >= 2.3) */
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#define SIBA_IM_RJ 0x02000000 /* reject (sonics >= 2.3) */
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/* sbtmstatelow */
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#define SIBA_TML_RESET 0x0001 /* reset */
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#define SIBA_TML_REJ_MASK 0x0006 /* reject field */
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#define SIBA_TML_REJ 0x0002 /* reject */
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#define SIBA_TML_TMPREJ 0x0004 /* temporary reject, for error recovery */
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#define SIBA_TML_SICF_MASK 0xFFFF0000 /* core IOCTL flags */
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#define SIBA_TML_SICF_SHIFT 16
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/* sbtmstatehigh */
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#define SIBA_TMH_SERR 0x0001 /* serror */
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#define SIBA_TMH_INT 0x0002 /* interrupt */
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#define SIBA_TMH_BUSY 0x0004 /* busy */
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#define SIBA_TMH_TO 0x0020 /* timeout (sonics >= 2.3) */
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#define SIBA_TMH_SISF_MASK 0xFFFF0000 /* core IOST flags */
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#define SIBA_TMH_SISF_SHIFT 16
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/* sbbwa0 */
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#define SIBA_BWA_TAB0_MASK 0xffff /* lookup table 0 */
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#define SIBA_BWA_TAB1_MASK 0xffff /* lookup table 1 */
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#define SIBA_BWA_TAB1_SHIFT 16
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/* sbimconfiglow */
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#define SIBA_IMCL_STO_MASK 0x7 /* service timeout */
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#define SIBA_IMCL_RTO_MASK 0x70 /* request timeout */
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#define SIBA_IMCL_RTO_SHIFT 4
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#define SIBA_IMCL_CID_MASK 0xff0000 /* connection id */
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#define SIBA_IMCL_CID_SHIFT 16
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/* sbimconfighigh */
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#define SIBA_IMCH_IEM_MASK 0xc /* inband error mode */
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#define SIBA_IMCH_TEM_MASK 0x30 /* timeout error mode */
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#define SIBA_IMCH_TEM_SHIFT 4
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#define SIBA_IMCH_BEM_MASK 0xc0 /* bus error mode */
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#define SIBA_IMCH_BEM_SHIFT 6
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/* sbadmatch0-4 */
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#define SIBA_AM_TYPE_MASK 0x3 /* address type */
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#define SIBA_AM_TYPE_SHIFT 0x0
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#define SIBA_AM_AD64 0x4 /* reserved */
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#define SIBA_AM_ADINT0_MASK 0xf8 /* type0 size */
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#define SIBA_AM_ADINT0_SHIFT 3
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#define SIBA_AM_ADINT1_MASK 0x1f8 /* type1 size */
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#define SIBA_AM_ADINT1_SHIFT 3
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#define SIBA_AM_ADINT2_MASK 0x1f8 /* type2 size */
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#define SIBA_AM_ADINT2_SHIFT 3
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#define SIBA_AM_ADEN 0x400 /* enable */
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#define SIBA_AM_ADNEG 0x800 /* negative decode */
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#define SIBA_AM_BASE0_MASK 0xffffff00 /* type0 base address */
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#define SIBA_AM_BASE0_SHIFT 8
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#define SIBA_AM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
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#define SIBA_AM_BASE1_SHIFT 12
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#define SIBA_AM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
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#define SIBA_AM_BASE2_SHIFT 16
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/* sbtmconfiglow */
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#define SIBA_TMCL_CD_MASK 0xff /* clock divide */
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#define SIBA_TMCL_CO_MASK 0xf800 /* clock offset */
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#define SIBA_TMCL_CO_SHIFT 11
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#define SIBA_TMCL_IF_MASK 0xfc0000 /* interrupt flags */
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#define SIBA_TMCL_IF_SHIFT 18
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#define SIBA_TMCL_IM_MASK 0x3000000 /* interrupt mode */
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#define SIBA_TMCL_IM_SHIFT 24
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/* sbtmconfighigh */
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#define SIBA_TMCH_BM_MASK 0x3 /* busy mode */
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#define SIBA_TMCH_RM_MASK 0x3 /* retry mode */
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#define SIBA_TMCH_RM_SHIFT 2
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#define SIBA_TMCH_SM_MASK 0x30 /* stop mode */
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#define SIBA_TMCH_SM_SHIFT 4
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#define SIBA_TMCH_EM_MASK 0x300 /* sb error mode */
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#define SIBA_TMCH_EM_SHIFT 8
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#define SIBA_TMCH_IM_MASK 0xc00 /* int mode */
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#define SIBA_TMCH_IM_SHIFT 10
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/* sbbconfig */
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#define SIBA_BC_LAT_MASK 0x3 /* sb latency */
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#define SIBA_BC_MAX0_MASK 0xf0000 /* maxccntr0 */
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#define SIBA_BC_MAX0_SHIFT 16
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#define SIBA_BC_MAX1_MASK 0xf00000 /* maxccntr1 */
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#define SIBA_BC_MAX1_SHIFT 20
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/* sbbstate */
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#define SIBA_BS_SRD 0x1 /* st reg disable */
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#define SIBA_BS_HRD 0x2 /* hold reg disable */
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/* sbidlow */
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#define SIBA_IDL_CS_MASK 0x3 /* config space */
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#define SIBA_IDL_CS_SHIFT 0
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#define SIBA_IDL_NRADDR_MASK 0x38 /* # address ranges supported */
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#define SIBA_IDL_NRADDR_SHIFT 3
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#define SIBA_IDL_SYNCH 0x40 /* sync */
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#define SIBA_IDL_INIT 0x80 /* initiator */
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#define SIBA_IDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
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#define SIBA_IDL_MINLAT_SHIFT 8
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#define SIBA_IDL_MAXLAT_MASK 0xf000 /* maximum backplane latency */
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#define SIBA_IDL_MAXLAT_SHIFT 12
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#define SIBA_IDL_FIRST_MASK 0x10000 /* this initiator is first */
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#define SIBA_IDL_FIRST_SHIFT 16
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#define SIBA_IDL_CW_MASK 0xc0000 /* cycle counter width */
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#define SIBA_IDL_CW_SHIFT 18
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#define SIBA_IDL_TP_MASK 0xf00000 /* target ports */
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#define SIBA_IDL_TP_SHIFT 20
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#define SIBA_IDL_IP_MASK 0xf000000 /* initiator ports */
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#define SIBA_IDL_IP_SHIFT 24
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#define SIBA_IDL_SBREV_MASK 0xf0000000 /* sonics backplane revision code */
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#define SIBA_IDL_SBREV_SHIFT 28
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#define SIBA_IDL_SBREV_2_2 0x0 /* version 2.2 or earlier */
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#define SIBA_IDL_SBREV_2_3 0x1 /* version 2.3 */
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/* sbidhigh */
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#define SIBA_IDH_RC_MASK 0x000f /* revision code */
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#define SIBA_IDH_RCE_MASK 0x7000 /* revision code extension field */
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#define SIBA_IDH_RCE_SHIFT 8
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#define SIBA_IDH_DEVICE_MASK 0x8ff0 /* core code */
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#define SIBA_IDH_DEVICE_SHIFT 4
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#define SIBA_IDH_VENDOR_MASK 0xffff0000 /* vendor code */
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#define SIBA_IDH_VENDOR_SHIFT 16
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#define SIBA_IDH_CORE_REV(sbidh) \
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(SIBA_REG_GET((sbidh), IDH_RCE) | ((sbidh) & SIBA_IDH_RC_MASK))
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#define SIBA_COMMIT 0xfd8 /* update buffered registers value */
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#endif /* _BHND_SIBA_SIBAREG_ */
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