Warner Losh c46a4f9afd Careful measurement of the ST Labs card shows that the pulse width of ... transmitted bits was between 8.6180us and 8.6200us when we used a RCLK of 16.500MHz. This is a little low (should be 8.6805us). This error is exactly the error one would expect if it actually had a 16.384MHz watch oscillator (as suggested by garrett) instead of using the PCI RCLK. Assume that the pci clock therefore wasn't really used, but instead the cheap 16.384MH watch quartz oscillator. This gives bits in the 8.6800us to 8.6810us ranage, which matches theoretical. Submitted by: garrett		2005-12-08 22:29:42 +00:00
..
puc_ebus.c
puc_pccard.c
puc_pci.c
puc_sbus.c
puc.c
pucdata.c	Careful measurement of the ST Labs card shows that the pulse width of	2005-12-08 22:29:42 +00:00
pucvar.h