3e9a516ed4
at91_machdep.c, and do it for the files I forgot the first time Reported by: andrew Submitted by: pluknet
524 lines
15 KiB
C
524 lines
15 KiB
C
/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */
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/*-
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* machdep.c
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*
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* Machine dependant functions for kernel setup
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*
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* This file needs a lot of work.
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*
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* Created : 17/09/94
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*/
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#include "opt_ddb.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define _ARM32_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysproto.h>
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#include <sys/signalvar.h>
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#include <sys/imgact.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/linker.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/ptrace.h>
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#include <sys/cons.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/buf.h>
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#include <sys/exec.h>
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#include <sys/kdb.h>
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#include <sys/msgbuf.h>
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#include <machine/reg.h>
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#include <machine/cpu.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <vm/vm_pager.h>
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#include <vm/vm_map.h>
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#include <vm/vnode_pager.h>
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#include <machine/pmap.h>
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#include <machine/vmparam.h>
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#include <machine/pcb.h>
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#include <machine/undefined.h>
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#include <machine/machdep.h>
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#include <machine/metadata.h>
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#include <machine/armreg.h>
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#include <machine/bus.h>
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#include <sys/reboot.h>
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#include <arm/xscale/pxa/pxareg.h>
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#include <arm/xscale/pxa/pxavar.h>
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#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
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#define KERNEL_PT_IOPXS 1
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#define KERNEL_PT_BEFOREKERN 2
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#define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */
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#define KERNEL_PT_AFKERNEL_NUM 9
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/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
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#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
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/* Define various stack sizes in pages */
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#define IRQ_STACK_SIZE 1
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#define ABT_STACK_SIZE 1
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#define UND_STACK_SIZE 1
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extern u_int data_abort_handler_address;
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extern u_int prefetch_abort_handler_address;
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extern u_int undefined_handler_address;
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struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
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extern void *_end;
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extern int *end;
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struct pcpu __pcpu;
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struct pcpu *pcpup = &__pcpu;
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/* Physical and virtual addresses for some global pages */
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vm_paddr_t phys_avail[PXA2X0_SDRAM_BANKS * 2 + 4];
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vm_paddr_t dump_avail[PXA2X0_SDRAM_BANKS * 2 + 4];
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vm_offset_t physical_pages;
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struct pv_addr systempage;
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struct pv_addr msgbufpv;
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struct pv_addr irqstack;
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struct pv_addr undstack;
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struct pv_addr abtstack;
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struct pv_addr kernelstack;
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struct pv_addr minidataclean;
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static struct trapframe proc0_tf;
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static void pxa_probe_sdram(bus_space_tag_t, bus_space_handle_t,
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uint32_t *, uint32_t *);
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/* Static device mappings. */
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static const struct pmap_devmap pxa_devmap[] = {
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/*
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* Map the on-board devices up into the KVA region so we don't muck
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* up user-space.
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*/
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{
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PXA2X0_PERIPH_START + PXA2X0_PERIPH_OFFSET,
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PXA2X0_PERIPH_START,
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PXA250_PERIPH_END - PXA2X0_PERIPH_START,
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VM_PROT_READ|VM_PROT_WRITE,
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PTE_NOCACHE,
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},
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{ 0, 0, 0, 0, 0, }
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};
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#define SDRAM_START 0xa0000000
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extern vm_offset_t xscale_cache_clean_addr;
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void *
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initarm(void *arg, void *arg2)
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{
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struct pv_addr kernel_l1pt;
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struct pv_addr dpcpu;
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int loop;
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u_int l1pagetable;
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vm_offset_t freemempos;
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vm_offset_t freemem_pt;
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vm_offset_t afterkern;
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vm_offset_t freemem_after;
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vm_offset_t lastaddr;
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int i, j;
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uint32_t memsize[PXA2X0_SDRAM_BANKS], memstart[PXA2X0_SDRAM_BANKS];
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set_cpufuncs();
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lastaddr = fake_preload_metadata();
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pcpu_init(pcpup, 0, sizeof(struct pcpu));
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PCPU_SET(curthread, &thread0);
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/* Do basic tuning, hz etc */
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init_param1();
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freemempos = 0xa0200000;
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/* Define a macro to simplify memory allocation */
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#define valloc_pages(var, np) \
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alloc_pages((var).pv_pa, (np)); \
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(var).pv_va = (var).pv_pa + 0x20000000;
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#define alloc_pages(var, np) \
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freemempos -= (np * PAGE_SIZE); \
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(var) = freemempos; \
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memset((char *)(var), 0, ((np) * PAGE_SIZE));
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while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
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freemempos -= PAGE_SIZE;
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valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
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for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
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if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
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valloc_pages(kernel_pt_table[loop],
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L2_TABLE_SIZE / PAGE_SIZE);
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} else {
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kernel_pt_table[loop].pv_pa = freemempos +
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(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
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L2_TABLE_SIZE_REAL;
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kernel_pt_table[loop].pv_va =
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kernel_pt_table[loop].pv_pa + 0x20000000;
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}
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i++;
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}
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freemem_pt = freemempos;
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freemempos = 0xa0100000;
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/*
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* Allocate a page for the system page mapped to V0x00000000
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* This page will just contain the system vectors and can be
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* shared by all processes.
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*/
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valloc_pages(systempage, 1);
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/* Allocate dynamic per-cpu area. */
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valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
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dpcpu_init((void *)dpcpu.pv_va, 0);
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/* Allocate stacks for all modes */
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valloc_pages(irqstack, IRQ_STACK_SIZE);
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valloc_pages(abtstack, ABT_STACK_SIZE);
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valloc_pages(undstack, UND_STACK_SIZE);
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valloc_pages(kernelstack, KSTACK_PAGES);
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alloc_pages(minidataclean.pv_pa, 1);
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valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
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#ifdef ARM_USE_SMALL_ALLOC
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freemempos -= PAGE_SIZE;
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freemem_pt = trunc_page(freemem_pt);
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freemem_after = freemempos - ((freemem_pt - 0xa0100000) /
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PAGE_SIZE) * sizeof(struct arm_small_page);
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arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000)
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, (void *)0xc0100000, freemem_pt - 0xa0100000, 1);
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freemem_after -= ((freemem_after - 0xa0001000) / PAGE_SIZE) *
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sizeof(struct arm_small_page);
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arm_add_smallalloc_pages((void *)(freemem_after + 0x20000000)
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, (void *)0xc0001000, trunc_page(freemem_after) - 0xa0001000, 0);
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freemempos = trunc_page(freemem_after);
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freemempos -= PAGE_SIZE;
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#endif
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/*
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* Allocate memory for the l1 and l2 page tables. The scheme to avoid
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* wasting memory by allocating the l1pt on the first 16k memory was
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* taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
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* this to work (which is supposed to be the case).
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*/
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/*
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* Now we start construction of the L1 page table
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* We start by mapping the L2 page tables into the L1.
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* This means that we can replace L1 mappings later on if necessary
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*/
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l1pagetable = kernel_l1pt.pv_va;
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/* Map the L2 pages tables in the L1 page table */
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pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
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&kernel_pt_table[KERNEL_PT_SYS]);
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#if 0 /* XXXBJR: What is this? Don't know if there's an analogue. */
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pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
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&kernel_pt_table[KERNEL_PT_IOPXS]);
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#endif
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pmap_link_l2pt(l1pagetable, KERNBASE,
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&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
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pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000,
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000,
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0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
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pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000,
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(((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
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afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) &
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~(L1_S_SIZE - 1));
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for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
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pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
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&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
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}
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pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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#ifdef ARM_USE_SMALL_ALLOC
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if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) {
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arm_add_smallalloc_pages((void *)(freemem_after),
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(void*)(freemem_after + PAGE_SIZE),
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afterkern - (freemem_after + PAGE_SIZE), 0);
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}
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#endif
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/* Map the Mini-Data cache clean area. */
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xscale_setup_minidata(l1pagetable, afterkern,
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minidataclean.pv_pa);
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/* Map the vector page. */
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pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
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VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
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pmap_devmap_bootstrap(l1pagetable, pxa_devmap);
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/*
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* Give the XScale global cache clean code an appropriately
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* sized chunk of unmapped VA space starting at 0xff000000
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* (our device mappings end before this address).
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*/
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xscale_cache_clean_addr = 0xff000000U;
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cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
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setttb(kernel_l1pt.pv_pa);
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cpu_tlb_flushID();
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cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
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/*
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* Pages were allocated during the secondary bootstrap for the
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* stacks for different CPU modes.
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* We must now set the r13 registers in the different CPU modes to
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* point to these stacks.
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* Since the ARM stacks use STMFD etc. we must set r13 to the top end
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* of the stack memory.
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*/
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set_stackptr(PSR_IRQ32_MODE,
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irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
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set_stackptr(PSR_ABT32_MODE,
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abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
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set_stackptr(PSR_UND32_MODE,
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undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
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/*
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* We must now clean the cache again....
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* Cleaning may be done by reading new data to displace any
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* dirty data in the cache. This will have happened in setttb()
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* but since we are boot strapping the addresses used for the read
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* may have just been remapped and thus the cache could be out
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* of sync. A re-clean after the switch will cure this.
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* After booting there are no gross relocations of the kernel thus
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* this problem will not occur after initarm().
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*/
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cpu_idcache_wbinv_all();
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/*
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* Sort out bus_space for on-board devices.
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*/
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pxa_obio_tag_init();
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/*
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* Fetch the SDRAM start/size from the PXA2X0 SDRAM configration
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* registers.
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*/
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pxa_probe_sdram(obio_tag, PXA2X0_MEMCTL_BASE, memstart, memsize);
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physmem = 0;
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for (i = 0; i < PXA2X0_SDRAM_BANKS; i++) {
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physmem += memsize[i] / PAGE_SIZE;
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}
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/* Fire up consoles. */
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cninit();
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/* Set stack for exception handlers */
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data_abort_handler_address = (u_int)data_abort_handler;
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prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
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undefined_handler_address = (u_int)undefinedinstruction_bounce;
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undefined_init();
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proc_linkup(&proc0, &thread0);
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thread0.td_kstack = kernelstack.pv_va;
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thread0.td_pcb = (struct pcb *)
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(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
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thread0.td_pcb->pcb_flags = 0;
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thread0.td_frame = &proc0_tf;
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pcpup->pc_curpcb = thread0.td_pcb;
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/* Enable MMU, I-cache, D-cache, write buffer. */
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arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
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pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
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/*
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* ARM USE_SMALL_ALLOC uses dump_avail, so it must be filled before
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* calling pmap_bootstrap.
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*/
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i = 0;
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for (j = 0; j < PXA2X0_SDRAM_BANKS; j++) {
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if (memsize[j] > 0) {
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dump_avail[i++] = round_page(memstart[j]);
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dump_avail[i++] =
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trunc_page(memstart[j] + memsize[j]);
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}
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}
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dump_avail[i] = 0;
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dump_avail[i] = 0;
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pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt);
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msgbufp = (void*)msgbufpv.pv_va;
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msgbufinit(msgbufp, msgbufsize);
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mutex_init();
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i = 0;
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#ifdef ARM_USE_SMALL_ALLOC
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phys_avail[i++] = 0xa0000000;
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phys_avail[i++] = 0xa0001000; /*
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*XXX: Gross hack to get our
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* pages in the vm_page_array
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. */
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#endif
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for (j = 0; j < PXA2X0_SDRAM_BANKS; j++) {
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if (memsize[j] > 0) {
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phys_avail[i] = round_page(memstart[j]);
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dump_avail[i++] = round_page(memstart[j]);
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phys_avail[i] =
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trunc_page(memstart[j] + memsize[j]);
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dump_avail[i++] =
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trunc_page(memstart[j] + memsize[j]);
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}
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}
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dump_avail[i] = 0;
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phys_avail[i++] = 0;
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dump_avail[i] = 0;
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phys_avail[i] = 0;
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#ifdef ARM_USE_SMALL_ALLOC
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phys_avail[2] = round_page(virtual_avail - KERNBASE + phys_avail[2]);
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#else
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phys_avail[0] = round_page(virtual_avail - KERNBASE + phys_avail[0]);
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#endif
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init_param2(physmem);
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kdb_init();
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return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
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sizeof(struct pcb)));
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}
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static void
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pxa_probe_sdram(bus_space_tag_t bst, bus_space_handle_t bsh,
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uint32_t *memstart, uint32_t *memsize)
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{
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uint32_t mdcnfg, dwid, dcac, drac, dnb;
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int i;
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mdcnfg = bus_space_read_4(bst, bsh, MEMCTL_MDCNFG);
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/*
|
|
* Scan all 4 SDRAM banks
|
|
*/
|
|
for (i = 0; i < PXA2X0_SDRAM_BANKS; i++) {
|
|
memstart[i] = 0;
|
|
memsize[i] = 0;
|
|
|
|
switch (i) {
|
|
case 0:
|
|
case 1:
|
|
if ((i == 0 && (mdcnfg & MDCNFG_DE0) == 0) ||
|
|
(i == 1 && (mdcnfg & MDCNFG_DE1) == 0))
|
|
continue;
|
|
dwid = mdcnfg >> MDCNFD_DWID01_SHIFT;
|
|
dcac = mdcnfg >> MDCNFD_DCAC01_SHIFT;
|
|
drac = mdcnfg >> MDCNFD_DRAC01_SHIFT;
|
|
dnb = mdcnfg >> MDCNFD_DNB01_SHIFT;
|
|
break;
|
|
|
|
case 2:
|
|
case 3:
|
|
if ((i == 2 && (mdcnfg & MDCNFG_DE2) == 0) ||
|
|
(i == 3 && (mdcnfg & MDCNFG_DE3) == 0))
|
|
continue;
|
|
dwid = mdcnfg >> MDCNFD_DWID23_SHIFT;
|
|
dcac = mdcnfg >> MDCNFD_DCAC23_SHIFT;
|
|
drac = mdcnfg >> MDCNFD_DRAC23_SHIFT;
|
|
dnb = mdcnfg >> MDCNFD_DNB23_SHIFT;
|
|
break;
|
|
default:
|
|
panic("pxa_probe_sdram: impossible");
|
|
}
|
|
|
|
dwid = 2 << (1 - (dwid & MDCNFD_DWID_MASK)); /* 16/32 width */
|
|
dcac = 1 << ((dcac & MDCNFD_DCAC_MASK) + 8); /* 8-11 columns */
|
|
drac = 1 << ((drac & MDCNFD_DRAC_MASK) + 11); /* 11-13 rows */
|
|
dnb = 2 << (dnb & MDCNFD_DNB_MASK); /* # of banks */
|
|
|
|
memsize[i] = dwid * dcac * drac * dnb;
|
|
memstart[i] = PXA2X0_SDRAM0_START +
|
|
(i * PXA2X0_SDRAM_BANK_SIZE);
|
|
}
|
|
}
|
|
|
|
#define TIMER_FREQUENCY 3686400
|
|
#define UNIMPLEMENTED panic("%s: unimplemented", __func__)
|
|
|
|
/* XXXBJR: Belongs with DELAY in a timer.c of some sort. */
|
|
void
|
|
cpu_startprofclock(void)
|
|
{
|
|
UNIMPLEMENTED;
|
|
}
|
|
|
|
void
|
|
cpu_stopprofclock(void)
|
|
{
|
|
UNIMPLEMENTED;
|
|
}
|
|
|
|
static struct arm32_dma_range pxa_range = {
|
|
.dr_sysbase = 0,
|
|
.dr_busbase = 0,
|
|
.dr_len = ~0u,
|
|
};
|
|
|
|
struct arm32_dma_range *
|
|
bus_dma_get_range(void)
|
|
{
|
|
|
|
return (&pxa_range);
|
|
}
|
|
|
|
int
|
|
bus_dma_get_range_nb(void)
|
|
{
|
|
|
|
return (1);
|
|
}
|