2b8344b8fa
fixed-state media with parameters set via hints
and configure MAC accordingly to these parameters.
All the underlying PHY magic is done by boot manager
on startup. At the moment there is no proper way
to make active and control all PHYs simultaneously
from one MII bus and there is no way to associate
incoming/outgoing packet with specific PHY.
158 lines
4.7 KiB
C
158 lines
4.7 KiB
C
/*-
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* Copyright (c) 2009, Oleksandr Tymoshenko
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __IF_ARGEVAR_H__
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#define __IF_ARGEVAR_H__
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#define ARGE_NPHY 32
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#define ARGE_TX_RING_COUNT 128
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#define ARGE_RX_RING_COUNT 128
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#define ARGE_RX_DMA_SIZE ARGE_RX_RING_COUNT * sizeof(struct arge_desc)
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#define ARGE_TX_DMA_SIZE ARGE_TX_RING_COUNT * sizeof(struct arge_desc)
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#define ARGE_MAXFRAGS 8
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#define ARGE_RING_ALIGN sizeof(struct arge_desc)
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#define ARGE_RX_ALIGN sizeof(uint32_t)
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#define ARGE_MAXFRAGS 8
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#define ARGE_TX_RING_ADDR(sc, i) \
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((sc)->arge_rdata.arge_tx_ring_paddr + sizeof(struct arge_desc) * (i))
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#define ARGE_RX_RING_ADDR(sc, i) \
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((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i))
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#define ARGE_INC(x,y) (x) = (((x) + 1) % y)
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#define ARGE_MII_TIMEOUT 1000
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#define ARGE_LOCK(_sc) mtx_lock(&(_sc)->arge_mtx)
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#define ARGE_UNLOCK(_sc) mtx_unlock(&(_sc)->arge_mtx)
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#define ARGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->arge_mtx, MA_OWNED)
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/*
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* register space access macros
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*/
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#define ARGE_WRITE(sc, reg, val) do { \
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bus_write_4(sc->arge_res, (reg), (val)); \
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} while (0)
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#define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg))
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#define ARGE_SET_BITS(sc, reg, bits) \
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ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits))
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#define ARGE_CLEAR_BITS(sc, reg, bits) \
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ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits))
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/*
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* MII registers access macros
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*/
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#define ARGE_MII_READ(reg) \
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*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((AR71XX_MII_BASE + reg)))
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#define ARGE_MII_WRITE(reg, val) \
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*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((AR71XX_MII_BASE + reg))) = (val)
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#define ARGE_DESC_EMPTY (1 << 31)
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#define ARGE_DESC_MORE (1 << 24)
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#define ARGE_DESC_SIZE_MASK ((1 << 12) - 1)
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#define ARGE_DMASIZE(len) ((len) & ARGE_DESC_SIZE_MASK)
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struct arge_desc {
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uint32_t packet_addr;
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uint32_t packet_ctrl;
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uint32_t next_desc;
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uint32_t padding;
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};
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struct arge_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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};
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struct arge_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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struct arge_desc *desc;
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};
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struct arge_chain_data {
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bus_dma_tag_t arge_parent_tag;
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bus_dma_tag_t arge_tx_tag;
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struct arge_txdesc arge_txdesc[ARGE_TX_RING_COUNT];
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bus_dma_tag_t arge_rx_tag;
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struct arge_rxdesc arge_rxdesc[ARGE_RX_RING_COUNT];
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bus_dma_tag_t arge_tx_ring_tag;
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bus_dma_tag_t arge_rx_ring_tag;
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bus_dmamap_t arge_tx_ring_map;
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bus_dmamap_t arge_rx_ring_map;
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bus_dmamap_t arge_rx_sparemap;
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int arge_tx_pkts;
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int arge_tx_prod;
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int arge_tx_cons;
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int arge_tx_cnt;
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int arge_rx_cons;
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};
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struct arge_ring_data {
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struct arge_desc *arge_rx_ring;
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struct arge_desc *arge_tx_ring;
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bus_addr_t arge_rx_ring_paddr;
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bus_addr_t arge_tx_ring_paddr;
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};
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struct arge_softc {
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struct ifnet *arge_ifp; /* interface info */
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device_t arge_dev;
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struct ifmedia arge_ifmedia;
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/*
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* Media & duples settings for multiPHY MAC
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*/
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uint32_t arge_media_type;
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uint32_t arge_duplex_mode;
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struct resource *arge_res;
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int arge_rid;
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struct resource *arge_irq;
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void *arge_intrhand;
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device_t arge_miibus;
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bus_dma_tag_t arge_parent_tag;
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bus_dma_tag_t arge_tag;
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struct mtx arge_mtx;
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struct callout arge_stat_callout;
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struct task arge_link_task;
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struct arge_chain_data arge_cdata;
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struct arge_ring_data arge_rdata;
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int arge_link_status;
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int arge_detach;
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uint32_t arge_intr_status;
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int arge_mac_unit;
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int arge_phymask;
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uint32_t arge_ddr_flush_reg;
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uint32_t arge_pll_reg;
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uint32_t arge_pll_reg_shift;
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int arge_if_flags;
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};
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#endif /* __IF_ARGEVAR_H__ */
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