3c6e15bcee
controller. The controller is also known as L1E(AR8121) and L2E(AR8113/AR8114). Unlike its predecessor Attansic L1, AR8121/AR8113/AR8114 uses completely different Rx logic such that it requires separate driver. Datasheet for AR81xx is not available to open source driver writers but it shares large part of Tx and PHY logic of L1. I still don't understand some part of register meaning and some MAC statistics counters but the driver seems to have no critical issues for performance and stability. The AR81xx requires copy operation to pass received frames to upper stack such that ale(4) consumes a lot of CPU cycles than that of other controller. A couple of silicon bugs also adds more CPU cycles to address the known hardware bug. However, if you have fast CPU you can still saturate the link. Currently ale(4) supports the following hardware features. - MSI. - TCP Segmentation offload. - Hardware VLAN tag insertion/stripping with checksum offload. - Tx TCP/UDP checksum offload and Rx IP/TCP/UDP checksum offload. - Tx/Rx interrupt moderation. - Hardware statistics counters. - Jumbo frame. - WOL. AR81xx PCIe ethernet controllers are mainly found on ASUS EeePC or P5Q series of ASUS motherboards. Special thanks to Jeremy Chadwick who sent the hardware to me. Without his donation writing a driver for AR81xx would never have been possible. Big thanks to all people who reported feedback or tested patches. HW donated by: koitsu Tested by: bsam, Joao Barros <joao.barros <> gmail DOT com > Jan Henrik Sylvester <me <> janh DOT de > Ivan Brawley < ivan <> brawley DOT id DOT au >, CURRENT ML
253 lines
7.3 KiB
C
253 lines
7.3 KiB
C
/*-
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* Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_ALEVAR_H
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#define _IF_ALEVAR_H
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#define ALE_TX_RING_CNT 256 /* Should be multiple of 4. */
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#define ALE_TX_RING_CNT_MIN 32
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#define ALE_TX_RING_CNT_MAX 1020
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#define ALE_TX_RING_ALIGN 8
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#define ALE_RX_PAGE_ALIGN 32
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#define ALE_RX_PAGES 2
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#define ALE_CMB_ALIGN 32
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#define ALE_TSO_MAXSEGSIZE 4096
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#define ALE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
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#define ALE_MAXTXSEGS 32
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#define ALE_ADDR_LO(x) ((uint64_t) (x) & 0xFFFFFFFF)
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#define ALE_ADDR_HI(x) ((uint64_t) (x) >> 32)
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/* Water mark to kick reclaiming Tx buffers. */
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#define ALE_TX_DESC_HIWAT (ALE_TX_RING_CNT - ((ALE_TX_RING_CNT * 4) / 10))
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#define ALE_MSI_MESSAGES 1
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#define ALE_MSIX_MESSAGES 1
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/*
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* TODO : Should get real jumbo MTU size.
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* The hardware seems to have trouble in dealing with large
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* frame length. If you encounter unstability issue, use
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* lower MTU size.
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*/
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#define ALE_JUMBO_FRAMELEN 8132
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#define ALE_JUMBO_MTU \
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(ALE_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - ETHER_CRC_LEN)
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#define ALE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)
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#define ALE_DESC_INC(x, y) ((x) = ((x) + 1) % (y))
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struct ale_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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};
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struct ale_rx_page {
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bus_dma_tag_t page_tag;
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bus_dmamap_t page_map;
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uint8_t *page_addr;
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bus_addr_t page_paddr;
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bus_dma_tag_t cmb_tag;
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bus_dmamap_t cmb_map;
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uint32_t *cmb_addr;
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bus_addr_t cmb_paddr;
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uint32_t cons;
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};
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struct ale_chain_data{
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bus_dma_tag_t ale_parent_tag;
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bus_dma_tag_t ale_buffer_tag;
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bus_dma_tag_t ale_tx_tag;
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struct ale_txdesc ale_txdesc[ALE_TX_RING_CNT];
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bus_dma_tag_t ale_tx_ring_tag;
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bus_dmamap_t ale_tx_ring_map;
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bus_dma_tag_t ale_rx_mblock_tag[ALE_RX_PAGES];
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bus_dmamap_t ale_rx_mblock_map[ALE_RX_PAGES];
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struct tx_desc *ale_tx_ring;
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bus_addr_t ale_tx_ring_paddr;
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uint32_t *ale_tx_cmb;
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bus_addr_t ale_tx_cmb_paddr;
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bus_dma_tag_t ale_tx_cmb_tag;
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bus_dmamap_t ale_tx_cmb_map;
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uint32_t ale_tx_prod;
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uint32_t ale_tx_cons;
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int ale_tx_cnt;
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struct ale_rx_page ale_rx_page[ALE_RX_PAGES];
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int ale_rx_curp;
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uint16_t ale_rx_seqno;
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};
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#define ALE_TX_RING_SZ \
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(sizeof(struct tx_desc) * ALE_TX_RING_CNT)
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#define ALE_RX_PAGE_SZ_MIN (8 * 1024)
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#define ALE_RX_PAGE_SZ_MAX (1024 * 1024)
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#define ALE_RX_FRAMES_PAGE 128
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#define ALE_RX_PAGE_SZ \
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(roundup(ALE_MAX_FRAMELEN, ALE_RX_PAGE_ALIGN) * ALE_RX_FRAMES_PAGE)
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#define ALE_TX_CMB_SZ (sizeof(uint32_t))
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#define ALE_RX_CMB_SZ (sizeof(uint32_t))
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#define ALE_PROC_MIN (ALE_RX_FRAMES_PAGE / 4)
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#define ALE_PROC_MAX \
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((ALE_RX_PAGE_SZ * ALE_RX_PAGES) / ETHER_MAX_LEN)
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#define ALE_PROC_DEFAULT (ALE_PROC_MAX / 4)
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struct ale_hw_stats {
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/* Rx stats. */
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uint32_t rx_frames;
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uint32_t rx_bcast_frames;
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uint32_t rx_mcast_frames;
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uint32_t rx_pause_frames;
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uint32_t rx_control_frames;
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uint32_t rx_crcerrs;
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uint32_t rx_lenerrs;
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uint64_t rx_bytes;
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uint32_t rx_runts;
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uint32_t rx_fragments;
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uint32_t rx_pkts_64;
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uint32_t rx_pkts_65_127;
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uint32_t rx_pkts_128_255;
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uint32_t rx_pkts_256_511;
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uint32_t rx_pkts_512_1023;
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uint32_t rx_pkts_1024_1518;
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uint32_t rx_pkts_1519_max;
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uint32_t rx_pkts_truncated;
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uint32_t rx_fifo_oflows;
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uint32_t rx_rrs_errs;
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uint32_t rx_alignerrs;
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uint64_t rx_bcast_bytes;
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uint64_t rx_mcast_bytes;
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uint32_t rx_pkts_filtered;
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/* Tx stats. */
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uint32_t tx_frames;
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uint32_t tx_bcast_frames;
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uint32_t tx_mcast_frames;
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uint32_t tx_pause_frames;
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uint32_t tx_excess_defer;
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uint32_t tx_control_frames;
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uint32_t tx_deferred;
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uint64_t tx_bytes;
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uint32_t tx_pkts_64;
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uint32_t tx_pkts_65_127;
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uint32_t tx_pkts_128_255;
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uint32_t tx_pkts_256_511;
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uint32_t tx_pkts_512_1023;
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uint32_t tx_pkts_1024_1518;
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uint32_t tx_pkts_1519_max;
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uint32_t tx_single_colls;
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uint32_t tx_multi_colls;
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uint32_t tx_late_colls;
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uint32_t tx_excess_colls;
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uint32_t tx_abort;
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uint32_t tx_underrun;
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uint32_t tx_desc_underrun;
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uint32_t tx_lenerrs;
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uint32_t tx_pkts_truncated;
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uint64_t tx_bcast_bytes;
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uint64_t tx_mcast_bytes;
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/* Misc. */
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uint32_t reset_brk_seq;
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};
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/*
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* Software state per device.
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*/
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struct ale_softc {
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struct ifnet *ale_ifp;
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device_t ale_dev;
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device_t ale_miibus;
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struct resource *ale_res[1];
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struct resource_spec *ale_res_spec;
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struct resource *ale_irq[ALE_MSI_MESSAGES];
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struct resource_spec *ale_irq_spec;
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void *ale_intrhand[ALE_MSI_MESSAGES];
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int ale_rev;
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int ale_chip_rev;
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int ale_phyaddr;
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uint8_t ale_eaddr[ETHER_ADDR_LEN];
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uint32_t ale_dma_rd_burst;
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uint32_t ale_dma_wr_burst;
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int ale_flags;
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#define ALE_FLAG_PCIE 0x0001
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#define ALE_FLAG_PCIX 0x0002
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#define ALE_FLAG_MSI 0x0004
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#define ALE_FLAG_MSIX 0x0008
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#define ALE_FLAG_PMCAP 0x0010
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#define ALE_FLAG_FASTETHER 0x0020
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#define ALE_FLAG_JUMBO 0x0040
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#define ALE_FLAG_RXCSUM_BUG 0x0080
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#define ALE_FLAG_TXCSUM_BUG 0x0100
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#define ALE_FLAG_TXCMB_BUG 0x0200
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#define ALE_FLAG_DETACH 0x4000
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#define ALE_FLAG_LINK 0x8000
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struct callout ale_tick_ch;
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struct ale_hw_stats ale_stats;
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struct ale_chain_data ale_cdata;
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int ale_if_flags;
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int ale_watchdog_timer;
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int ale_process_limit;
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volatile int ale_morework;
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int ale_int_rx_mod;
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int ale_int_tx_mod;
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int ale_max_frame_size;
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int ale_pagesize;
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struct task ale_int_task;
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struct task ale_tx_task;
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struct task ale_link_task;
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struct taskqueue *ale_tq;
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struct mtx ale_mtx;
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};
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/* Register access macros. */
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#define CSR_WRITE_4(_sc, reg, val) \
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bus_write_4((_sc)->ale_res[0], (reg), (val))
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#define CSR_WRITE_2(_sc, reg, val) \
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bus_write_2((_sc)->ale_res[0], (reg), (val))
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#define CSR_WRITE_1(_sc, reg, val) \
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bus_write_1((_sc)->ale_res[0], (reg), (val))
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#define CSR_READ_2(_sc, reg) \
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bus_read_2((_sc)->ale_res[0], (reg))
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#define CSR_READ_4(_sc, reg) \
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bus_read_4((_sc)->ale_res[0], (reg))
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#define ALE_LOCK(_sc) mtx_lock(&(_sc)->ale_mtx)
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#define ALE_UNLOCK(_sc) mtx_unlock(&(_sc)->ale_mtx)
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#define ALE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ale_mtx, MA_OWNED)
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#define ALE_TX_TIMEOUT 5
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#define ALE_RESET_TIMEOUT 100
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#define ALE_TIMEOUT 1000
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#define ALE_PHY_TIMEOUT 1000
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#endif /* _IF_ATEVAR_H */
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