9467e3f3fc
Bus errors will show up as various SYNC interrupts which will be passed back up to ath_intr().
267 lines
11 KiB
C
267 lines
11 KiB
C
/*-
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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/*
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* Ioctl-related defintions for the Atheros Wireless LAN controller driver.
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*/
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#ifndef _DEV_ATH_ATHIOCTL_H
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#define _DEV_ATH_ATHIOCTL_H
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struct ath_tx_aggr_stats {
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u_int32_t aggr_pkts[64];
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u_int32_t aggr_single_pkt;
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u_int32_t aggr_nonbaw_pkt;
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u_int32_t aggr_aggr_pkt;
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u_int32_t aggr_baw_closed_single_pkt;
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u_int32_t aggr_low_hwq_single_pkt;
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u_int32_t aggr_sched_nopkt;
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u_int32_t aggr_rts_aggr_limited;
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};
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struct ath_intr_stats {
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u_int32_t sync_intr[32];
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};
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struct ath_stats {
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u_int32_t ast_watchdog; /* device reset by watchdog */
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u_int32_t ast_hardware; /* fatal hardware error interrupts */
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u_int32_t ast_bmiss; /* beacon miss interrupts */
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u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */
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u_int32_t ast_bstuck; /* beacon stuck interrupts */
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u_int32_t ast_rxorn; /* rx overrun interrupts */
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u_int32_t ast_rxeol; /* rx eol interrupts */
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u_int32_t ast_txurn; /* tx underrun interrupts */
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u_int32_t ast_mib; /* mib interrupts */
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u_int32_t ast_intrcoal; /* interrupts coalesced */
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u_int32_t ast_tx_packets; /* packet sent on the interface */
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u_int32_t ast_tx_mgmt; /* management frames transmitted */
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u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
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u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
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u_int32_t ast_tx_encap; /* tx encapsulation failed */
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u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
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u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
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u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
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u_int32_t ast_tx_linear; /* tx linearized to cluster */
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u_int32_t ast_tx_nodata; /* tx discarded empty frame */
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u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
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u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
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u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
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u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
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u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
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u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
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u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
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u_int32_t ast_tx_noack; /* tx frames with no ack marked */
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u_int32_t ast_tx_rts; /* tx frames with rts enabled */
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u_int32_t ast_tx_cts; /* tx frames with cts enabled */
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u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
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u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
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u_int32_t ast_tx_protect; /* tx frames with protection */
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u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */
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u_int32_t ast_tx_ctsext; /* tx frames with cts extension */
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u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
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u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
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u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
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u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
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u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
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u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
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u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */
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u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
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u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */
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u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
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u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
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u_int32_t ast_rx_packets; /* packet recv on the interface */
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u_int32_t ast_rx_mgt; /* management frames received */
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u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
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int8_t ast_tx_rssi; /* tx rssi of last ack */
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int8_t ast_rx_rssi; /* rx rssi from histogram */
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u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */
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u_int32_t ast_be_xmit; /* beacons transmitted */
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u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
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u_int32_t ast_per_cal; /* periodic calibration calls */
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u_int32_t ast_per_calfail;/* periodic calibration failed */
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u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
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u_int32_t ast_rate_calls; /* rate control checks */
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u_int32_t ast_rate_raise; /* rate control raised xmit rate */
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u_int32_t ast_rate_drop; /* rate control dropped xmit rate */
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u_int32_t ast_ant_defswitch;/* rx/default antenna switches */
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u_int32_t ast_ant_txswitch;/* tx antenna switches */
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u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
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u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
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u_int32_t ast_cabq_xmit; /* cabq frames transmitted */
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u_int32_t ast_cabq_busy; /* cabq found busy */
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u_int32_t ast_tx_raw; /* tx frames through raw api */
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u_int32_t ast_ff_txok; /* fast frames tx'd successfully */
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u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */
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u_int32_t ast_ff_rx; /* fast frames rx'd */
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u_int32_t ast_ff_flush; /* fast frames flushed from staging q */
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u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */
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int8_t ast_rx_noise; /* rx noise floor */
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u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */
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u_int32_t ast_tdma_update;/* TDMA slot timing updates */
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u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */
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u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */
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u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/
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u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/
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u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */
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u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */
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u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */
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u_int32_t ast_be_missed; /* missed beacons */
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u_int32_t ast_ani_cal; /* ANI calibrations performed */
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u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */
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u_int32_t ast_rx_halfgi; /* RX half-GI */
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u_int32_t ast_rx_2040; /* RX 40mhz frame */
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u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */
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u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */
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u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */
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u_int32_t ast_rx_hi_rx_chain;
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u_int32_t ast_tx_htprotect; /* HT tx frames with protection */
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u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */
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u_int32_t ast_tx_timeout; /* Global TX timeout */
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u_int32_t ast_tx_cst; /* Carrier sense timeout */
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u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */
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u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */
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u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */
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u_int32_t ast_tx_swretries; /* software TX retries */
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u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */
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u_int32_t ast_tx_data_underrun;
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u_int32_t ast_tx_delim_underrun;
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u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */
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u_int32_t ast_tx_getnobuf;
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u_int32_t ast_tx_getbusybuf;
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u_int32_t ast_tx_intr;
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u_int32_t ast_rx_intr;
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u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */
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u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */
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u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */
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u_int32_t ast_pad[1];
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};
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#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
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#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq)
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struct ath_diag {
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char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */
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u_int16_t ad_id;
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#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */
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#define ATH_DIAG_IN 0x4000 /* copy in parameters */
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#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */
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#define ATH_DIAG_ID 0x0fff
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u_int16_t ad_in_size; /* pack to fit, yech */
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caddr_t ad_in_data;
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caddr_t ad_out_data;
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u_int ad_out_size;
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};
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#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
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#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag)
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/*
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* Radio capture format.
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*/
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#define ATH_RX_RADIOTAP_PRESENT ( \
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(1 << IEEE80211_RADIOTAP_TSFT) | \
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(1 << IEEE80211_RADIOTAP_FLAGS) | \
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(1 << IEEE80211_RADIOTAP_RATE) | \
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(1 << IEEE80211_RADIOTAP_ANTENNA) | \
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(1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
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(1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \
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(1 << IEEE80211_RADIOTAP_XCHANNEL) | \
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0)
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struct ath_rx_radiotap_header {
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struct ieee80211_radiotap_header wr_ihdr;
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u_int64_t wr_tsf;
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u_int8_t wr_flags;
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u_int8_t wr_rate;
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int8_t wr_antsignal;
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int8_t wr_antnoise;
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u_int8_t wr_antenna;
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u_int8_t wr_pad[3];
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u_int32_t wr_chan_flags;
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u_int16_t wr_chan_freq;
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u_int8_t wr_chan_ieee;
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int8_t wr_chan_maxpow;
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} __packed;
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#define ATH_TX_RADIOTAP_PRESENT ( \
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(1 << IEEE80211_RADIOTAP_TSFT) | \
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(1 << IEEE80211_RADIOTAP_FLAGS) | \
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(1 << IEEE80211_RADIOTAP_RATE) | \
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(1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \
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(1 << IEEE80211_RADIOTAP_ANTENNA) | \
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(1 << IEEE80211_RADIOTAP_XCHANNEL) | \
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0)
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struct ath_tx_radiotap_header {
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struct ieee80211_radiotap_header wt_ihdr;
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u_int64_t wt_tsf;
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u_int8_t wt_flags;
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u_int8_t wt_rate;
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u_int8_t wt_txpower;
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u_int8_t wt_antenna;
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u_int32_t wt_chan_flags;
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u_int16_t wt_chan_freq;
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u_int8_t wt_chan_ieee;
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int8_t wt_chan_maxpow;
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} __packed;
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/*
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* DFS ioctl commands
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*/
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#define DFS_SET_THRESH 2
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#define DFS_GET_THRESH 3
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#define DFS_RADARDETECTS 6
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/*
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* DFS ioctl parameter types
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*/
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#define DFS_PARAM_FIRPWR 1
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#define DFS_PARAM_RRSSI 2
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#define DFS_PARAM_HEIGHT 3
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#define DFS_PARAM_PRSSI 4
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#define DFS_PARAM_INBAND 5
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#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */
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#define DFS_PARAM_RELSTEP_EN 7
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#define DFS_PARAM_RELSTEP 8
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#define DFS_PARAM_RELPWR_EN 9
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#define DFS_PARAM_RELPWR 10
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#define DFS_PARAM_MAXLEN 11
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#define DFS_PARAM_USEFIR128 12
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#define DFS_PARAM_BLOCKRADAR 13
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#define DFS_PARAM_MAXRSSI_EN 14
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/* FreeBSD-specific start at 32 */
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#define DFS_PARAM_ENABLE 32
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#define DFS_PARAM_EN_EXTCH 33
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#endif /* _DEV_ATH_ATHIOCTL_H */
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