1470 lines
52 KiB
C++
1470 lines
52 KiB
C++
//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of a target
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// register file for a code generator. It uses instances of the Register,
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// RegisterAliases, and RegisterClass classes to gather this information.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenRegisters.h"
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#include "CodeGenTarget.h"
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#include "SequenceToOffsetTable.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/Format.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <algorithm>
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#include <set>
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#include <vector>
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using namespace llvm;
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namespace {
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class RegisterInfoEmitter {
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RecordKeeper &Records;
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public:
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RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
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// runEnums - Print out enum values for all of the registers.
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void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
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// runMCDesc - Print out MC register descriptions.
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void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
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// runTargetHeader - Emit a header fragment for the register info emitter.
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void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
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CodeGenRegBank &Bank);
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// runTargetDesc - Output the target register and register file descriptions.
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void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
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CodeGenRegBank &Bank);
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// run - Output the register file description.
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void run(raw_ostream &o);
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private:
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void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
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bool isCtor);
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void EmitRegMappingTables(raw_ostream &o,
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const std::deque<CodeGenRegister> &Regs,
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bool isCtor);
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void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
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const std::string &ClassName);
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void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
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const std::string &ClassName);
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void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
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const std::string &ClassName);
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};
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} // End anonymous namespace
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// runEnums - Print out enum values for all of the registers.
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void RegisterInfoEmitter::runEnums(raw_ostream &OS,
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CodeGenTarget &Target, CodeGenRegBank &Bank) {
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const auto &Registers = Bank.getRegisters();
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// Register enums are stored as uint16_t in the tables. Make sure we'll fit.
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assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
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std::string Namespace =
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Registers.front().TheDef->getValueAsString("Namespace");
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emitSourceFileHeader("Target Register Enum Values", OS);
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OS << "\n#ifdef GET_REGINFO_ENUM\n";
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OS << "#undef GET_REGINFO_ENUM\n";
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OS << "namespace llvm {\n\n";
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OS << "class MCRegisterClass;\n"
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<< "extern const MCRegisterClass " << Namespace
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<< "MCRegisterClasses[];\n\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n NoRegister,\n";
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for (const auto &Reg : Registers)
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OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
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assert(Registers.size() == Registers.back().EnumValue &&
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"Register enum value mismatch!");
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OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
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OS << "};\n";
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if (!Namespace.empty())
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OS << "}\n";
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const auto &RegisterClasses = Bank.getRegClasses();
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if (!RegisterClasses.empty()) {
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// RegisterClass enums are stored as uint16_t in the tables.
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assert(RegisterClasses.size() <= 0xffff &&
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"Too many register classes to fit in tables");
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OS << "\n// Register classes\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n";
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for (const auto &RC : RegisterClasses)
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OS << " " << RC.getName() << "RegClassID"
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<< " = " << RC.EnumValue << ",\n";
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OS << "\n };\n";
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if (!Namespace.empty())
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OS << "}\n";
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}
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const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
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// If the only definition is the default NoRegAltName, we don't need to
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// emit anything.
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if (RegAltNameIndices.size() > 1) {
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OS << "\n// Register alternate name indices\n";
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n";
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for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
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OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
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OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
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OS << "};\n";
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if (!Namespace.empty())
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OS << "}\n";
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}
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auto &SubRegIndices = Bank.getSubRegIndices();
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if (!SubRegIndices.empty()) {
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OS << "\n// Subregister indices\n";
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std::string Namespace = SubRegIndices.front().getNamespace();
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if (!Namespace.empty())
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OS << "namespace " << Namespace << " {\n";
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OS << "enum {\n NoSubRegister,\n";
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unsigned i = 0;
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for (const auto &Idx : SubRegIndices)
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OS << " " << Idx.getName() << ",\t// " << ++i << "\n";
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OS << " NUM_TARGET_SUBREGS\n};\n";
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if (!Namespace.empty())
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OS << "}\n";
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}
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OS << "} // End llvm namespace\n";
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OS << "#endif // GET_REGINFO_ENUM\n\n";
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}
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static void printInt(raw_ostream &OS, int Val) {
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OS << Val;
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}
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static const char *getMinimalTypeForRange(uint64_t Range) {
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assert(Range < 0xFFFFFFFFULL && "Enum too large");
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if (Range > 0xFFFF)
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return "uint32_t";
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if (Range > 0xFF)
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return "uint16_t";
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return "uint8_t";
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}
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void RegisterInfoEmitter::
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EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
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const std::string &ClassName) {
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unsigned NumRCs = RegBank.getRegClasses().size();
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unsigned NumSets = RegBank.getNumRegPressureSets();
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OS << "/// Get the weight in units of pressure for this register class.\n"
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<< "const RegClassWeight &" << ClassName << "::\n"
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<< "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
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<< " static const RegClassWeight RCWeightTable[] = {\n";
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for (const auto &RC : RegBank.getRegClasses()) {
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const CodeGenRegister::Vec &Regs = RC.getMembers();
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if (Regs.empty())
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OS << " {0, 0";
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else {
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std::vector<unsigned> RegUnits;
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RC.buildRegUnitSet(RegUnits);
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OS << " {" << (*Regs.begin())->getWeight(RegBank)
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<< ", " << RegBank.getRegUnitSetWeight(RegUnits);
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}
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OS << "}, \t// " << RC.getName() << "\n";
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}
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OS << " };\n"
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<< " return RCWeightTable[RC->getID()];\n"
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<< "}\n\n";
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// Reasonable targets (not ARMv7) have unit weight for all units, so don't
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// bother generating a table.
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bool RegUnitsHaveUnitWeight = true;
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for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
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UnitIdx < UnitEnd; ++UnitIdx) {
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if (RegBank.getRegUnit(UnitIdx).Weight > 1)
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RegUnitsHaveUnitWeight = false;
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}
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OS << "/// Get the weight in units of pressure for this register unit.\n"
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<< "unsigned " << ClassName << "::\n"
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<< "getRegUnitWeight(unsigned RegUnit) const {\n"
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<< " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
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<< " && \"invalid register unit\");\n";
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if (!RegUnitsHaveUnitWeight) {
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OS << " static const uint8_t RUWeightTable[] = {\n ";
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for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
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UnitIdx < UnitEnd; ++UnitIdx) {
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const RegUnit &RU = RegBank.getRegUnit(UnitIdx);
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assert(RU.Weight < 256 && "RegUnit too heavy");
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OS << RU.Weight << ", ";
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}
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OS << "};\n"
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<< " return RUWeightTable[RegUnit];\n";
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}
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else {
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OS << " // All register units have unit weight.\n"
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<< " return 1;\n";
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}
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OS << "}\n\n";
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OS << "\n"
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<< "// Get the number of dimensions of register pressure.\n"
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<< "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
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<< " return " << NumSets << ";\n}\n\n";
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OS << "// Get the name of this register unit pressure set.\n"
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<< "const char *" << ClassName << "::\n"
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<< "getRegPressureSetName(unsigned Idx) const {\n"
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<< " static const char *const PressureNameTable[] = {\n";
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unsigned MaxRegUnitWeight = 0;
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for (unsigned i = 0; i < NumSets; ++i ) {
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const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
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MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight);
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OS << " \"" << RegUnits.Name << "\",\n";
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}
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OS << " nullptr };\n"
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<< " return PressureNameTable[Idx];\n"
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<< "}\n\n";
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OS << "// Get the register unit pressure limit for this dimension.\n"
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<< "// This limit must be adjusted dynamically for reserved registers.\n"
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<< "unsigned " << ClassName << "::\n"
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<< "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {\n"
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<< " static const " << getMinimalTypeForRange(MaxRegUnitWeight)
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<< " PressureLimitTable[] = {\n";
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for (unsigned i = 0; i < NumSets; ++i ) {
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const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
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OS << " " << RegUnits.Weight << ", \t// " << i << ": "
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<< RegUnits.Name << "\n";
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}
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OS << " };\n"
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<< " return PressureLimitTable[Idx];\n"
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<< "}\n\n";
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SequenceToOffsetTable<std::vector<int>> PSetsSeqs;
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// This table may be larger than NumRCs if some register units needed a list
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// of unit sets that did not correspond to a register class.
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unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists();
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std::vector<std::vector<int>> PSets(NumRCUnitSets);
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for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) {
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ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
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PSets[i].reserve(PSetIDs.size());
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for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
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PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
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PSets[i].push_back(RegBank.getRegPressureSet(*PSetI).Order);
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}
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std::sort(PSets[i].begin(), PSets[i].end());
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PSetsSeqs.add(PSets[i]);
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}
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PSetsSeqs.layout();
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OS << "/// Table of pressure sets per register class or unit.\n"
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<< "static const int RCSetsTable[] = {\n";
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PSetsSeqs.emit(OS, printInt, "-1");
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OS << "};\n\n";
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OS << "/// Get the dimensions of register pressure impacted by this "
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<< "register class.\n"
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<< "/// Returns a -1 terminated array of pressure set IDs\n"
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<< "const int* " << ClassName << "::\n"
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<< "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n";
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OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
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<< " RCSetStartTable[] = {\n ";
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for (unsigned i = 0, e = NumRCs; i != e; ++i) {
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OS << PSetsSeqs.get(PSets[i]) << ",";
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}
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OS << "};\n"
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<< " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n"
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<< "}\n\n";
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OS << "/// Get the dimensions of register pressure impacted by this "
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<< "register unit.\n"
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<< "/// Returns a -1 terminated array of pressure set IDs\n"
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<< "const int* " << ClassName << "::\n"
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<< "getRegUnitPressureSets(unsigned RegUnit) const {\n"
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<< " assert(RegUnit < " << RegBank.getNumNativeRegUnits()
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<< " && \"invalid register unit\");\n";
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OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1)
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<< " RUSetStartTable[] = {\n ";
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for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits();
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UnitIdx < UnitEnd; ++UnitIdx) {
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OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx])
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<< ",";
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}
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OS << "};\n"
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<< " return &RCSetsTable[RUSetStartTable[RegUnit]];\n"
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<< "}\n\n";
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}
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void RegisterInfoEmitter::EmitRegMappingTables(
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raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
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// Collect all information about dwarf register numbers
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typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
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DwarfRegNumsMapTy DwarfRegNums;
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// First, just pull all provided information to the map
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unsigned maxLength = 0;
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for (auto &RE : Regs) {
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Record *Reg = RE.TheDef;
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std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
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maxLength = std::max((size_t)maxLength, RegNums.size());
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if (DwarfRegNums.count(Reg))
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PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
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getQualifiedName(Reg) + "specified multiple times");
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DwarfRegNums[Reg] = RegNums;
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}
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if (!maxLength)
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return;
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// Now we know maximal length of number list. Append -1's, where needed
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for (DwarfRegNumsMapTy::iterator
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I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
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for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
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I->second.push_back(-1);
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std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
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OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
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// Emit reverse information about the dwarf register numbers.
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for (unsigned j = 0; j < 2; ++j) {
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for (unsigned i = 0, e = maxLength; i != e; ++i) {
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OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
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OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
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OS << i << "Dwarf2L[]";
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if (!isCtor) {
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OS << " = {\n";
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// Store the mapping sorted by the LLVM reg num so lookup can be done
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// with a binary search.
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std::map<uint64_t, Record*> Dwarf2LMap;
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for (DwarfRegNumsMapTy::iterator
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I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
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int DwarfRegNo = I->second[i];
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if (DwarfRegNo < 0)
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continue;
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Dwarf2LMap[DwarfRegNo] = I->first;
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}
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for (std::map<uint64_t, Record*>::iterator
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I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
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OS << " { " << I->first << "U, " << getQualifiedName(I->second)
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<< " },\n";
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OS << "};\n";
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} else {
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OS << ";\n";
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}
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// We have to store the size in a const global, it's used in multiple
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// places.
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OS << "extern const unsigned " << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
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if (!isCtor)
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OS << " = array_lengthof(" << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
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<< "Dwarf2L);\n\n";
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else
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OS << ";\n\n";
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}
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}
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for (auto &RE : Regs) {
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Record *Reg = RE.TheDef;
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const RecordVal *V = Reg->getValue("DwarfAlias");
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if (!V || !V->getValue())
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continue;
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DefInit *DI = cast<DefInit>(V->getValue());
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Record *Alias = DI->getDef();
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DwarfRegNums[Reg] = DwarfRegNums[Alias];
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}
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// Emit information about the dwarf register numbers.
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for (unsigned j = 0; j < 2; ++j) {
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for (unsigned i = 0, e = maxLength; i != e; ++i) {
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OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
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OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
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OS << i << "L2Dwarf[]";
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if (!isCtor) {
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OS << " = {\n";
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// Store the mapping sorted by the Dwarf reg num so lookup can be done
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// with a binary search.
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for (DwarfRegNumsMapTy::iterator
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I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
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int RegNo = I->second[i];
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if (RegNo == -1) // -1 is the default value, don't emit a mapping.
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continue;
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OS << " { " << getQualifiedName(I->first) << ", " << RegNo
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<< "U },\n";
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}
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OS << "};\n";
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} else {
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OS << ";\n";
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}
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// We have to store the size in a const global, it's used in multiple
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// places.
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OS << "extern const unsigned " << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
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if (!isCtor)
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OS << " = array_lengthof(" << Namespace
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<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n";
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else
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OS << ";\n\n";
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}
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}
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}
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void RegisterInfoEmitter::EmitRegMapping(
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raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {
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// Emit the initializer so the tables from EmitRegMappingTables get wired up
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// to the MCRegisterInfo object.
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unsigned maxLength = 0;
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for (auto &RE : Regs) {
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Record *Reg = RE.TheDef;
|
|
maxLength = std::max((size_t)maxLength,
|
|
Reg->getValueAsListOfInts("DwarfNumbers").size());
|
|
}
|
|
|
|
if (!maxLength)
|
|
return;
|
|
|
|
std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
|
|
|
|
// Emit reverse information about the dwarf register numbers.
|
|
for (unsigned j = 0; j < 2; ++j) {
|
|
OS << " switch (";
|
|
if (j == 0)
|
|
OS << "DwarfFlavour";
|
|
else
|
|
OS << "EHFlavour";
|
|
OS << ") {\n"
|
|
<< " default:\n"
|
|
<< " llvm_unreachable(\"Unknown DWARF flavour\");\n";
|
|
|
|
for (unsigned i = 0, e = maxLength; i != e; ++i) {
|
|
OS << " case " << i << ":\n";
|
|
OS << " ";
|
|
if (!isCtor)
|
|
OS << "RI->";
|
|
std::string Tmp;
|
|
raw_string_ostream(Tmp) << Namespace
|
|
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
|
|
<< "Dwarf2L";
|
|
OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
|
|
if (j == 0)
|
|
OS << "false";
|
|
else
|
|
OS << "true";
|
|
OS << ");\n";
|
|
OS << " break;\n";
|
|
}
|
|
OS << " }\n";
|
|
}
|
|
|
|
// Emit information about the dwarf register numbers.
|
|
for (unsigned j = 0; j < 2; ++j) {
|
|
OS << " switch (";
|
|
if (j == 0)
|
|
OS << "DwarfFlavour";
|
|
else
|
|
OS << "EHFlavour";
|
|
OS << ") {\n"
|
|
<< " default:\n"
|
|
<< " llvm_unreachable(\"Unknown DWARF flavour\");\n";
|
|
|
|
for (unsigned i = 0, e = maxLength; i != e; ++i) {
|
|
OS << " case " << i << ":\n";
|
|
OS << " ";
|
|
if (!isCtor)
|
|
OS << "RI->";
|
|
std::string Tmp;
|
|
raw_string_ostream(Tmp) << Namespace
|
|
<< (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
|
|
<< "L2Dwarf";
|
|
OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
|
|
if (j == 0)
|
|
OS << "false";
|
|
else
|
|
OS << "true";
|
|
OS << ");\n";
|
|
OS << " break;\n";
|
|
}
|
|
OS << " }\n";
|
|
}
|
|
}
|
|
|
|
// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
|
|
// Width is the number of bits per hex number.
|
|
static void printBitVectorAsHex(raw_ostream &OS,
|
|
const BitVector &Bits,
|
|
unsigned Width) {
|
|
assert(Width <= 32 && "Width too large");
|
|
unsigned Digits = (Width + 3) / 4;
|
|
for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
|
|
unsigned Value = 0;
|
|
for (unsigned j = 0; j != Width && i + j != e; ++j)
|
|
Value |= Bits.test(i + j) << j;
|
|
OS << format("0x%0*x, ", Digits, Value);
|
|
}
|
|
}
|
|
|
|
// Helper to emit a set of bits into a constant byte array.
|
|
class BitVectorEmitter {
|
|
BitVector Values;
|
|
public:
|
|
void add(unsigned v) {
|
|
if (v >= Values.size())
|
|
Values.resize(((v/8)+1)*8); // Round up to the next byte.
|
|
Values[v] = true;
|
|
}
|
|
|
|
void print(raw_ostream &OS) {
|
|
printBitVectorAsHex(OS, Values, 8);
|
|
}
|
|
};
|
|
|
|
static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
|
|
OS << getEnumName(VT);
|
|
}
|
|
|
|
static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
|
|
OS << Idx->EnumValue;
|
|
}
|
|
|
|
// Differentially encoded register and regunit lists allow for better
|
|
// compression on regular register banks. The sequence is computed from the
|
|
// differential list as:
|
|
//
|
|
// out[0] = InitVal;
|
|
// out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
|
|
//
|
|
// The initial value depends on the specific list. The list is terminated by a
|
|
// 0 differential which means we can't encode repeated elements.
|
|
|
|
typedef SmallVector<uint16_t, 4> DiffVec;
|
|
typedef SmallVector<unsigned, 4> MaskVec;
|
|
|
|
// Differentially encode a sequence of numbers into V. The starting value and
|
|
// terminating 0 are not added to V, so it will have the same size as List.
|
|
static
|
|
DiffVec &diffEncode(DiffVec &V, unsigned InitVal, SparseBitVector<> List) {
|
|
assert(V.empty() && "Clear DiffVec before diffEncode.");
|
|
uint16_t Val = uint16_t(InitVal);
|
|
|
|
for (uint16_t Cur : List) {
|
|
V.push_back(Cur - Val);
|
|
Val = Cur;
|
|
}
|
|
return V;
|
|
}
|
|
|
|
template<typename Iter>
|
|
static
|
|
DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) {
|
|
assert(V.empty() && "Clear DiffVec before diffEncode.");
|
|
uint16_t Val = uint16_t(InitVal);
|
|
for (Iter I = Begin; I != End; ++I) {
|
|
uint16_t Cur = (*I)->EnumValue;
|
|
V.push_back(Cur - Val);
|
|
Val = Cur;
|
|
}
|
|
return V;
|
|
}
|
|
|
|
static void printDiff16(raw_ostream &OS, uint16_t Val) {
|
|
OS << Val;
|
|
}
|
|
|
|
static void printMask(raw_ostream &OS, unsigned Val) {
|
|
OS << format("0x%08X", Val);
|
|
}
|
|
|
|
// Try to combine Idx's compose map into Vec if it is compatible.
|
|
// Return false if it's not possible.
|
|
static bool combine(const CodeGenSubRegIndex *Idx,
|
|
SmallVectorImpl<CodeGenSubRegIndex*> &Vec) {
|
|
const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites();
|
|
for (const auto &I : Map) {
|
|
CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1];
|
|
if (Entry && Entry != I.second)
|
|
return false;
|
|
}
|
|
|
|
// All entries are compatible. Make it so.
|
|
for (const auto &I : Map) {
|
|
auto *&Entry = Vec[I.first->EnumValue - 1];
|
|
assert((!Entry || Entry == I.second) &&
|
|
"Expected EnumValue to be unique");
|
|
Entry = I.second;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
void
|
|
RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
|
|
CodeGenRegBank &RegBank,
|
|
const std::string &ClName) {
|
|
const auto &SubRegIndices = RegBank.getSubRegIndices();
|
|
OS << "unsigned " << ClName
|
|
<< "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
|
|
|
|
// Many sub-register indexes are composition-compatible, meaning that
|
|
//
|
|
// compose(IdxA, IdxB) == compose(IdxA', IdxB)
|
|
//
|
|
// for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed.
|
|
// The illegal entries can be use as wildcards to compress the table further.
|
|
|
|
// Map each Sub-register index to a compatible table row.
|
|
SmallVector<unsigned, 4> RowMap;
|
|
SmallVector<SmallVector<CodeGenSubRegIndex*, 4>, 4> Rows;
|
|
|
|
auto SubRegIndicesSize =
|
|
std::distance(SubRegIndices.begin(), SubRegIndices.end());
|
|
for (const auto &Idx : SubRegIndices) {
|
|
unsigned Found = ~0u;
|
|
for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
|
|
if (combine(&Idx, Rows[r])) {
|
|
Found = r;
|
|
break;
|
|
}
|
|
}
|
|
if (Found == ~0u) {
|
|
Found = Rows.size();
|
|
Rows.resize(Found + 1);
|
|
Rows.back().resize(SubRegIndicesSize);
|
|
combine(&Idx, Rows.back());
|
|
}
|
|
RowMap.push_back(Found);
|
|
}
|
|
|
|
// Output the row map if there is multiple rows.
|
|
if (Rows.size() > 1) {
|
|
OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap["
|
|
<< SubRegIndicesSize << "] = {\n ";
|
|
for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
|
|
OS << RowMap[i] << ", ";
|
|
OS << "\n };\n";
|
|
}
|
|
|
|
// Output the rows.
|
|
OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1)
|
|
<< " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n";
|
|
for (unsigned r = 0, re = Rows.size(); r != re; ++r) {
|
|
OS << " { ";
|
|
for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i)
|
|
if (Rows[r][i])
|
|
OS << Rows[r][i]->EnumValue << ", ";
|
|
else
|
|
OS << "0, ";
|
|
OS << "},\n";
|
|
}
|
|
OS << " };\n\n";
|
|
|
|
OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n"
|
|
<< " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n";
|
|
if (Rows.size() > 1)
|
|
OS << " return Rows[RowMap[IdxA]][IdxB];\n";
|
|
else
|
|
OS << " return Rows[0][IdxB];\n";
|
|
OS << "}\n\n";
|
|
}
|
|
|
|
void
|
|
RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
|
|
CodeGenRegBank &RegBank,
|
|
const std::string &ClName) {
|
|
// See the comments in computeSubRegLaneMasks() for our goal here.
|
|
const auto &SubRegIndices = RegBank.getSubRegIndices();
|
|
|
|
// Create a list of Mask+Rotate operations, with equivalent entries merged.
|
|
SmallVector<unsigned, 4> SubReg2SequenceIndexMap;
|
|
SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences;
|
|
for (const auto &Idx : SubRegIndices) {
|
|
const SmallVector<MaskRolPair, 1> &IdxSequence
|
|
= Idx.CompositionLaneMaskTransform;
|
|
|
|
unsigned Found = ~0u;
|
|
unsigned SIdx = 0;
|
|
unsigned NextSIdx;
|
|
for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) {
|
|
SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
|
|
NextSIdx = SIdx + Sequence.size() + 1;
|
|
if (Sequence == IdxSequence) {
|
|
Found = SIdx;
|
|
break;
|
|
}
|
|
}
|
|
if (Found == ~0u) {
|
|
Sequences.push_back(IdxSequence);
|
|
Found = SIdx;
|
|
}
|
|
SubReg2SequenceIndexMap.push_back(Found);
|
|
}
|
|
|
|
OS << "unsigned " << ClName
|
|
<< "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, unsigned LaneMask)"
|
|
" const {\n";
|
|
|
|
OS << " struct MaskRolOp {\n"
|
|
" unsigned Mask;\n"
|
|
" uint8_t RotateLeft;\n"
|
|
" };\n"
|
|
" static const MaskRolOp Seqs[] = {\n";
|
|
unsigned Idx = 0;
|
|
for (size_t s = 0, se = Sequences.size(); s != se; ++s) {
|
|
OS << " ";
|
|
const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
|
|
for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) {
|
|
const MaskRolPair &P = Sequence[p];
|
|
OS << format("{ 0x%08X, %2u }, ", P.Mask, P.RotateLeft);
|
|
}
|
|
OS << "{ 0, 0 }";
|
|
if (s+1 != se)
|
|
OS << ", ";
|
|
OS << " // Sequence " << Idx << "\n";
|
|
Idx += Sequence.size() + 1;
|
|
}
|
|
OS << " };\n"
|
|
" static const MaskRolOp *const CompositeSequences[] = {\n";
|
|
for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) {
|
|
OS << " ";
|
|
unsigned Idx = SubReg2SequenceIndexMap[i];
|
|
OS << format("&Seqs[%u]", Idx);
|
|
if (i+1 != e)
|
|
OS << ",";
|
|
OS << " // to " << SubRegIndices[i].getName() << "\n";
|
|
}
|
|
OS << " };\n\n";
|
|
|
|
OS << " --IdxA; assert(IdxA < " << SubRegIndices.size()
|
|
<< " && \"Subregister index out of bounds\");\n"
|
|
" unsigned Result = 0;\n"
|
|
" for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask != 0; ++Ops)"
|
|
" {\n"
|
|
" unsigned Masked = LaneMask & Ops->Mask;\n"
|
|
" Result |= (Masked << Ops->RotateLeft) & 0xFFFFFFFF;\n"
|
|
" Result |= (Masked >> ((32 - Ops->RotateLeft) & 0x1F));\n"
|
|
" }\n"
|
|
" return Result;\n"
|
|
"}\n";
|
|
}
|
|
|
|
//
|
|
// runMCDesc - Print out MC register descriptions.
|
|
//
|
|
void
|
|
RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|
CodeGenRegBank &RegBank) {
|
|
emitSourceFileHeader("MC Register Information", OS);
|
|
|
|
OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
|
|
OS << "#undef GET_REGINFO_MC_DESC\n";
|
|
|
|
const auto &Regs = RegBank.getRegisters();
|
|
|
|
auto &SubRegIndices = RegBank.getSubRegIndices();
|
|
// The lists of sub-registers and super-registers go in the same array. That
|
|
// allows us to share suffixes.
|
|
typedef std::vector<const CodeGenRegister*> RegVec;
|
|
|
|
// Differentially encoded lists.
|
|
SequenceToOffsetTable<DiffVec> DiffSeqs;
|
|
SmallVector<DiffVec, 4> SubRegLists(Regs.size());
|
|
SmallVector<DiffVec, 4> SuperRegLists(Regs.size());
|
|
SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
|
|
SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
|
|
|
|
// List of lane masks accompanying register unit sequences.
|
|
SequenceToOffsetTable<MaskVec> LaneMaskSeqs;
|
|
SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());
|
|
|
|
// Keep track of sub-register names as well. These are not differentially
|
|
// encoded.
|
|
typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
|
|
SequenceToOffsetTable<SubRegIdxVec, deref<llvm::less>> SubRegIdxSeqs;
|
|
SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
|
|
|
|
SequenceToOffsetTable<std::string> RegStrings;
|
|
|
|
// Precompute register lists for the SequenceToOffsetTable.
|
|
unsigned i = 0;
|
|
for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {
|
|
const auto &Reg = *I;
|
|
RegStrings.add(Reg.getName());
|
|
|
|
// Compute the ordered sub-register list.
|
|
SetVector<const CodeGenRegister*> SR;
|
|
Reg.addSubRegsPreOrder(SR, RegBank);
|
|
diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end());
|
|
DiffSeqs.add(SubRegLists[i]);
|
|
|
|
// Compute the corresponding sub-register indexes.
|
|
SubRegIdxVec &SRIs = SubRegIdxLists[i];
|
|
for (unsigned j = 0, je = SR.size(); j != je; ++j)
|
|
SRIs.push_back(Reg.getSubRegIndex(SR[j]));
|
|
SubRegIdxSeqs.add(SRIs);
|
|
|
|
// Super-registers are already computed.
|
|
const RegVec &SuperRegList = Reg.getSuperRegs();
|
|
diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(),
|
|
SuperRegList.end());
|
|
DiffSeqs.add(SuperRegLists[i]);
|
|
|
|
// Differentially encode the register unit list, seeded by register number.
|
|
// First compute a scale factor that allows more diff-lists to be reused:
|
|
//
|
|
// D0 -> (S0, S1)
|
|
// D1 -> (S2, S3)
|
|
//
|
|
// A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
|
|
// value for the differential decoder is the register number multiplied by
|
|
// the scale.
|
|
//
|
|
// Check the neighboring registers for arithmetic progressions.
|
|
unsigned ScaleA = ~0u, ScaleB = ~0u;
|
|
SparseBitVector<> RUs = Reg.getNativeRegUnits();
|
|
if (I != Regs.begin() &&
|
|
std::prev(I)->getNativeRegUnits().count() == RUs.count())
|
|
ScaleB = *RUs.begin() - *std::prev(I)->getNativeRegUnits().begin();
|
|
if (std::next(I) != Regs.end() &&
|
|
std::next(I)->getNativeRegUnits().count() == RUs.count())
|
|
ScaleA = *std::next(I)->getNativeRegUnits().begin() - *RUs.begin();
|
|
unsigned Scale = std::min(ScaleB, ScaleA);
|
|
// Default the scale to 0 if it can't be encoded in 4 bits.
|
|
if (Scale >= 16)
|
|
Scale = 0;
|
|
RegUnitInitScale[i] = Scale;
|
|
DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg.EnumValue, RUs));
|
|
|
|
const auto &RUMasks = Reg.getRegUnitLaneMasks();
|
|
MaskVec &LaneMaskVec = RegUnitLaneMasks[i];
|
|
assert(LaneMaskVec.empty());
|
|
LaneMaskVec.insert(LaneMaskVec.begin(), RUMasks.begin(), RUMasks.end());
|
|
// Terminator mask should not be used inside of the list.
|
|
#ifndef NDEBUG
|
|
for (unsigned M : LaneMaskVec) {
|
|
assert(M != ~0u && "terminator mask should not be part of the list");
|
|
}
|
|
#endif
|
|
LaneMaskSeqs.add(LaneMaskVec);
|
|
}
|
|
|
|
// Compute the final layout of the sequence table.
|
|
DiffSeqs.layout();
|
|
LaneMaskSeqs.layout();
|
|
SubRegIdxSeqs.layout();
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
const std::string &TargetName = Target.getName();
|
|
|
|
// Emit the shared table of differential lists.
|
|
OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n";
|
|
DiffSeqs.emit(OS, printDiff16);
|
|
OS << "};\n\n";
|
|
|
|
// Emit the shared table of regunit lane mask sequences.
|
|
OS << "extern const unsigned " << TargetName << "LaneMaskLists[] = {\n";
|
|
LaneMaskSeqs.emit(OS, printMask, "~0u");
|
|
OS << "};\n\n";
|
|
|
|
// Emit the table of sub-register indexes.
|
|
OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n";
|
|
SubRegIdxSeqs.emit(OS, printSubRegIndex);
|
|
OS << "};\n\n";
|
|
|
|
// Emit the table of sub-register index sizes.
|
|
OS << "extern const MCRegisterInfo::SubRegCoveredBits "
|
|
<< TargetName << "SubRegIdxRanges[] = {\n";
|
|
OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
|
|
for (const auto &Idx : SubRegIndices) {
|
|
OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// "
|
|
<< Idx.getName() << "\n";
|
|
}
|
|
OS << "};\n\n";
|
|
|
|
// Emit the string table.
|
|
RegStrings.layout();
|
|
OS << "extern const char " << TargetName << "RegStrings[] = {\n";
|
|
RegStrings.emit(OS, printChar);
|
|
OS << "};\n\n";
|
|
|
|
OS << "extern const MCRegisterDesc " << TargetName
|
|
<< "RegDesc[] = { // Descriptors\n";
|
|
OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n";
|
|
|
|
// Emit the register descriptors now.
|
|
i = 0;
|
|
for (const auto &Reg : Regs) {
|
|
OS << " { " << RegStrings.get(Reg.getName()) << ", "
|
|
<< DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
|
|
<< ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
|
|
<< (DiffSeqs.get(RegUnitLists[i]) * 16 + RegUnitInitScale[i]) << ", "
|
|
<< LaneMaskSeqs.get(RegUnitLaneMasks[i]) << " },\n";
|
|
++i;
|
|
}
|
|
OS << "};\n\n"; // End of register descriptors...
|
|
|
|
// Emit the table of register unit roots. Each regunit has one or two root
|
|
// registers.
|
|
OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
|
|
for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
|
|
ArrayRef<const CodeGenRegister*> Roots = RegBank.getRegUnit(i).getRoots();
|
|
assert(!Roots.empty() && "All regunits must have a root register.");
|
|
assert(Roots.size() <= 2 && "More than two roots not supported yet.");
|
|
OS << " { " << getQualifiedName(Roots.front()->TheDef);
|
|
for (unsigned r = 1; r != Roots.size(); ++r)
|
|
OS << ", " << getQualifiedName(Roots[r]->TheDef);
|
|
OS << " },\n";
|
|
}
|
|
OS << "};\n\n";
|
|
|
|
const auto &RegisterClasses = RegBank.getRegClasses();
|
|
|
|
// Loop over all of the register classes... emitting each one.
|
|
OS << "namespace { // Register classes...\n";
|
|
|
|
SequenceToOffsetTable<std::string> RegClassStrings;
|
|
|
|
// Emit the register enum value arrays for each RegisterClass
|
|
for (const auto &RC : RegisterClasses) {
|
|
ArrayRef<Record*> Order = RC.getOrder();
|
|
|
|
// Give the register class a legal C name if it's anonymous.
|
|
std::string Name = RC.getName();
|
|
|
|
RegClassStrings.add(Name);
|
|
|
|
// Emit the register list now.
|
|
OS << " // " << Name << " Register Class...\n"
|
|
<< " const MCPhysReg " << Name
|
|
<< "[] = {\n ";
|
|
for (unsigned i = 0, e = Order.size(); i != e; ++i) {
|
|
Record *Reg = Order[i];
|
|
OS << getQualifiedName(Reg) << ", ";
|
|
}
|
|
OS << "\n };\n\n";
|
|
|
|
OS << " // " << Name << " Bit set.\n"
|
|
<< " const uint8_t " << Name
|
|
<< "Bits[] = {\n ";
|
|
BitVectorEmitter BVE;
|
|
for (unsigned i = 0, e = Order.size(); i != e; ++i) {
|
|
Record *Reg = Order[i];
|
|
BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
|
|
}
|
|
BVE.print(OS);
|
|
OS << "\n };\n\n";
|
|
|
|
}
|
|
OS << "}\n\n";
|
|
|
|
RegClassStrings.layout();
|
|
OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
|
|
RegClassStrings.emit(OS, printChar);
|
|
OS << "};\n\n";
|
|
|
|
OS << "extern const MCRegisterClass " << TargetName
|
|
<< "MCRegisterClasses[] = {\n";
|
|
|
|
for (const auto &RC : RegisterClasses) {
|
|
// Asserts to make sure values will fit in table assuming types from
|
|
// MCRegisterInfo.h
|
|
assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
|
|
assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
|
|
assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
|
|
|
|
OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, "
|
|
<< RegClassStrings.get(RC.getName()) << ", "
|
|
<< RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
|
|
<< RC.getQualifiedName() + "RegClassID" << ", "
|
|
<< RC.SpillSize/8 << ", "
|
|
<< RC.SpillAlignment/8 << ", "
|
|
<< RC.CopyCost << ", "
|
|
<< RC.Allocatable << " },\n";
|
|
}
|
|
|
|
OS << "};\n\n";
|
|
|
|
EmitRegMappingTables(OS, Regs, false);
|
|
|
|
// Emit Reg encoding table
|
|
OS << "extern const uint16_t " << TargetName;
|
|
OS << "RegEncodingTable[] = {\n";
|
|
// Add entry for NoRegister
|
|
OS << " 0,\n";
|
|
for (const auto &RE : Regs) {
|
|
Record *Reg = RE.TheDef;
|
|
BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
|
|
uint64_t Value = 0;
|
|
for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
|
|
if (BitInit *B = dyn_cast<BitInit>(BI->getBit(b)))
|
|
Value |= (uint64_t)B->getValue() << b;
|
|
}
|
|
OS << " " << Value << ",\n";
|
|
}
|
|
OS << "};\n"; // End of HW encoding table
|
|
|
|
// MCRegisterInfo initialization routine.
|
|
OS << "static inline void Init" << TargetName
|
|
<< "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
|
|
<< "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) "
|
|
"{\n"
|
|
<< " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
|
|
<< Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
|
|
<< RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
|
|
<< RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, "
|
|
<< TargetName << "LaneMaskLists, " << TargetName << "RegStrings, "
|
|
<< TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, "
|
|
<< (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
|
|
<< TargetName << "SubRegIdxRanges, " << TargetName
|
|
<< "RegEncodingTable);\n\n";
|
|
|
|
EmitRegMapping(OS, Regs, false);
|
|
|
|
OS << "}\n\n";
|
|
|
|
OS << "} // End llvm namespace\n";
|
|
OS << "#endif // GET_REGINFO_MC_DESC\n\n";
|
|
}
|
|
|
|
void
|
|
RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
|
|
CodeGenRegBank &RegBank) {
|
|
emitSourceFileHeader("Register Information Header Fragment", OS);
|
|
|
|
OS << "\n#ifdef GET_REGINFO_HEADER\n";
|
|
OS << "#undef GET_REGINFO_HEADER\n";
|
|
|
|
const std::string &TargetName = Target.getName();
|
|
std::string ClassName = TargetName + "GenRegisterInfo";
|
|
|
|
OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
|
|
<< " explicit " << ClassName
|
|
<< "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
|
|
<< " bool needsStackRealignment(const MachineFunction &) const override\n"
|
|
<< " { return false; }\n";
|
|
if (!RegBank.getSubRegIndices().empty()) {
|
|
OS << " unsigned composeSubRegIndicesImpl"
|
|
<< "(unsigned, unsigned) const override;\n"
|
|
<< " unsigned composeSubRegIndexLaneMaskImpl"
|
|
<< "(unsigned, unsigned) const override;\n"
|
|
<< " const TargetRegisterClass *getSubClassWithSubReg"
|
|
<< "(const TargetRegisterClass*, unsigned) const override;\n";
|
|
}
|
|
OS << " const RegClassWeight &getRegClassWeight("
|
|
<< "const TargetRegisterClass *RC) const override;\n"
|
|
<< " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
|
|
<< " unsigned getNumRegPressureSets() const override;\n"
|
|
<< " const char *getRegPressureSetName(unsigned Idx) const override;\n"
|
|
<< " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned "
|
|
"Idx) const override;\n"
|
|
<< " const int *getRegClassPressureSets("
|
|
<< "const TargetRegisterClass *RC) const override;\n"
|
|
<< " const int *getRegUnitPressureSets("
|
|
<< "unsigned RegUnit) const override;\n"
|
|
<< "};\n\n";
|
|
|
|
const auto &RegisterClasses = RegBank.getRegClasses();
|
|
|
|
if (!RegisterClasses.empty()) {
|
|
OS << "namespace " << RegisterClasses.front().Namespace
|
|
<< " { // Register classes\n";
|
|
|
|
for (const auto &RC : RegisterClasses) {
|
|
const std::string &Name = RC.getName();
|
|
|
|
// Output the extern for the instance.
|
|
OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
|
|
}
|
|
OS << "} // end of namespace " << TargetName << "\n\n";
|
|
}
|
|
OS << "} // End llvm namespace\n";
|
|
OS << "#endif // GET_REGINFO_HEADER\n\n";
|
|
}
|
|
|
|
//
|
|
// runTargetDesc - Output the target register and register file descriptions.
|
|
//
|
|
void
|
|
RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|
CodeGenRegBank &RegBank){
|
|
emitSourceFileHeader("Target Register and Register Classes Information", OS);
|
|
|
|
OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
|
|
OS << "#undef GET_REGINFO_TARGET_DESC\n";
|
|
|
|
OS << "namespace llvm {\n\n";
|
|
|
|
// Get access to MCRegisterClass data.
|
|
OS << "extern const MCRegisterClass " << Target.getName()
|
|
<< "MCRegisterClasses[];\n";
|
|
|
|
// Start out by emitting each of the register classes.
|
|
const auto &RegisterClasses = RegBank.getRegClasses();
|
|
const auto &SubRegIndices = RegBank.getSubRegIndices();
|
|
|
|
// Collect all registers belonging to any allocatable class.
|
|
std::set<Record*> AllocatableRegs;
|
|
|
|
// Collect allocatable registers.
|
|
for (const auto &RC : RegisterClasses) {
|
|
ArrayRef<Record*> Order = RC.getOrder();
|
|
|
|
if (RC.Allocatable)
|
|
AllocatableRegs.insert(Order.begin(), Order.end());
|
|
}
|
|
|
|
// Build a shared array of value types.
|
|
SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs;
|
|
for (const auto &RC : RegisterClasses)
|
|
VTSeqs.add(RC.VTs);
|
|
VTSeqs.layout();
|
|
OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
|
|
VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
|
|
OS << "};\n";
|
|
|
|
// Emit SubRegIndex names, skipping 0.
|
|
OS << "\nstatic const char *const SubRegIndexNameTable[] = { \"";
|
|
|
|
for (const auto &Idx : SubRegIndices) {
|
|
OS << Idx.getName();
|
|
OS << "\", \"";
|
|
}
|
|
OS << "\" };\n\n";
|
|
|
|
// Emit SubRegIndex lane masks, including 0.
|
|
OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n";
|
|
for (const auto &Idx : SubRegIndices) {
|
|
OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n';
|
|
}
|
|
OS << " };\n\n";
|
|
|
|
OS << "\n";
|
|
|
|
// Now that all of the structs have been emitted, emit the instances.
|
|
if (!RegisterClasses.empty()) {
|
|
OS << "\nstatic const TargetRegisterClass *const "
|
|
<< "NullRegClasses[] = { nullptr };\n\n";
|
|
|
|
// Emit register class bit mask tables. The first bit mask emitted for a
|
|
// register class, RC, is the set of sub-classes, including RC itself.
|
|
//
|
|
// If RC has super-registers, also create a list of subreg indices and bit
|
|
// masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
|
|
// SuperRC, that satisfies:
|
|
//
|
|
// For all SuperReg in SuperRC: SuperReg:Idx in RC
|
|
//
|
|
// The 0-terminated list of subreg indices starts at:
|
|
//
|
|
// RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
|
|
//
|
|
// The corresponding bitmasks follow the sub-class mask in memory. Each
|
|
// mask has RCMaskWords uint32_t entries.
|
|
//
|
|
// Every bit mask present in the list has at least one bit set.
|
|
|
|
// Compress the sub-reg index lists.
|
|
typedef std::vector<const CodeGenSubRegIndex*> IdxList;
|
|
SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
|
|
SequenceToOffsetTable<IdxList, deref<llvm::less>> SuperRegIdxSeqs;
|
|
BitVector MaskBV(RegisterClasses.size());
|
|
|
|
for (const auto &RC : RegisterClasses) {
|
|
OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n ";
|
|
printBitVectorAsHex(OS, RC.getSubClasses(), 32);
|
|
|
|
// Emit super-reg class masks for any relevant SubRegIndices that can
|
|
// project into RC.
|
|
IdxList &SRIList = SuperRegIdxLists[RC.EnumValue];
|
|
for (auto &Idx : SubRegIndices) {
|
|
MaskBV.reset();
|
|
RC.getSuperRegClasses(&Idx, MaskBV);
|
|
if (MaskBV.none())
|
|
continue;
|
|
SRIList.push_back(&Idx);
|
|
OS << "\n ";
|
|
printBitVectorAsHex(OS, MaskBV, 32);
|
|
OS << "// " << Idx.getName();
|
|
}
|
|
SuperRegIdxSeqs.add(SRIList);
|
|
OS << "\n};\n\n";
|
|
}
|
|
|
|
OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
|
|
SuperRegIdxSeqs.layout();
|
|
SuperRegIdxSeqs.emit(OS, printSubRegIndex);
|
|
OS << "};\n\n";
|
|
|
|
// Emit NULL terminated super-class lists.
|
|
for (const auto &RC : RegisterClasses) {
|
|
ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
|
|
|
|
// Skip classes without supers. We can reuse NullRegClasses.
|
|
if (Supers.empty())
|
|
continue;
|
|
|
|
OS << "static const TargetRegisterClass *const "
|
|
<< RC.getName() << "Superclasses[] = {\n";
|
|
for (const auto *Super : Supers)
|
|
OS << " &" << Super->getQualifiedName() << "RegClass,\n";
|
|
OS << " nullptr\n};\n\n";
|
|
}
|
|
|
|
// Emit methods.
|
|
for (const auto &RC : RegisterClasses) {
|
|
if (!RC.AltOrderSelect.empty()) {
|
|
OS << "\nstatic inline unsigned " << RC.getName()
|
|
<< "AltOrderSelect(const MachineFunction &MF) {"
|
|
<< RC.AltOrderSelect << "}\n\n"
|
|
<< "static ArrayRef<MCPhysReg> " << RC.getName()
|
|
<< "GetRawAllocationOrder(const MachineFunction &MF) {\n";
|
|
for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
|
|
ArrayRef<Record*> Elems = RC.getOrder(oi);
|
|
if (!Elems.empty()) {
|
|
OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
|
|
for (unsigned elem = 0; elem != Elems.size(); ++elem)
|
|
OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
|
|
OS << " };\n";
|
|
}
|
|
}
|
|
OS << " const MCRegisterClass &MCR = " << Target.getName()
|
|
<< "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
|
|
<< " const ArrayRef<MCPhysReg> Order[] = {\n"
|
|
<< " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
|
|
for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
|
|
if (RC.getOrder(oi).empty())
|
|
OS << "),\n ArrayRef<MCPhysReg>(";
|
|
else
|
|
OS << "),\n makeArrayRef(AltOrder" << oi;
|
|
OS << ")\n };\n const unsigned Select = " << RC.getName()
|
|
<< "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
|
|
<< ");\n return Order[Select];\n}\n";
|
|
}
|
|
}
|
|
|
|
// Now emit the actual value-initialized register class instances.
|
|
OS << "\nnamespace " << RegisterClasses.front().Namespace
|
|
<< " { // Register class instances\n";
|
|
|
|
for (const auto &RC : RegisterClasses) {
|
|
OS << " extern const TargetRegisterClass " << RC.getName()
|
|
<< "RegClass = {\n " << '&' << Target.getName()
|
|
<< "MCRegisterClasses[" << RC.getName() << "RegClassID],\n "
|
|
<< "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName()
|
|
<< "SubClassMask,\n SuperRegIdxSeqs + "
|
|
<< SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "
|
|
<< format("0x%08x,\n ", RC.LaneMask)
|
|
<< (unsigned)RC.AllocationPriority << ",\n "
|
|
<< (RC.HasDisjunctSubRegs?"true":"false")
|
|
<< ", /* HasDisjunctSubRegs */\n ";
|
|
if (RC.getSuperClasses().empty())
|
|
OS << "NullRegClasses,\n ";
|
|
else
|
|
OS << RC.getName() << "Superclasses,\n ";
|
|
if (RC.AltOrderSelect.empty())
|
|
OS << "nullptr\n";
|
|
else
|
|
OS << RC.getName() << "GetRawAllocationOrder\n";
|
|
OS << " };\n\n";
|
|
}
|
|
|
|
OS << "}\n";
|
|
}
|
|
|
|
OS << "\nnamespace {\n";
|
|
OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
|
|
for (const auto &RC : RegisterClasses)
|
|
OS << " &" << RC.getQualifiedName() << "RegClass,\n";
|
|
OS << " };\n";
|
|
OS << "}\n"; // End of anonymous namespace...
|
|
|
|
// Emit extra information about registers.
|
|
const std::string &TargetName = Target.getName();
|
|
OS << "\nstatic const TargetRegisterInfoDesc "
|
|
<< TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
|
|
OS << " { 0, 0 },\n";
|
|
|
|
const auto &Regs = RegBank.getRegisters();
|
|
for (const auto &Reg : Regs) {
|
|
OS << " { ";
|
|
OS << Reg.CostPerUse << ", "
|
|
<< int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
|
|
}
|
|
OS << "};\n"; // End of register descriptors...
|
|
|
|
|
|
std::string ClassName = Target.getName() + "GenRegisterInfo";
|
|
|
|
auto SubRegIndicesSize =
|
|
std::distance(SubRegIndices.begin(), SubRegIndices.end());
|
|
|
|
if (!SubRegIndices.empty()) {
|
|
emitComposeSubRegIndices(OS, RegBank, ClassName);
|
|
emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);
|
|
}
|
|
|
|
// Emit getSubClassWithSubReg.
|
|
if (!SubRegIndices.empty()) {
|
|
OS << "const TargetRegisterClass *" << ClassName
|
|
<< "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
|
|
<< " const {\n";
|
|
// Use the smallest type that can hold a regclass ID with room for a
|
|
// sentinel.
|
|
if (RegisterClasses.size() < UINT8_MAX)
|
|
OS << " static const uint8_t Table[";
|
|
else if (RegisterClasses.size() < UINT16_MAX)
|
|
OS << " static const uint16_t Table[";
|
|
else
|
|
PrintFatalError("Too many register classes.");
|
|
OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
|
|
for (const auto &RC : RegisterClasses) {
|
|
OS << " {\t// " << RC.getName() << "\n";
|
|
for (auto &Idx : SubRegIndices) {
|
|
if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
|
|
OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
|
|
<< " -> " << SRC->getName() << "\n";
|
|
else
|
|
OS << " 0,\t// " << Idx.getName() << "\n";
|
|
}
|
|
OS << " },\n";
|
|
}
|
|
OS << " };\n assert(RC && \"Missing regclass\");\n"
|
|
<< " if (!Idx) return RC;\n --Idx;\n"
|
|
<< " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
|
|
<< " unsigned TV = Table[RC->getID()][Idx];\n"
|
|
<< " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
|
|
}
|
|
|
|
EmitRegUnitPressure(OS, RegBank, ClassName);
|
|
|
|
// Emit the constructor of the class...
|
|
OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
|
|
OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
|
|
OS << "extern const unsigned " << TargetName << "LaneMaskLists[];\n";
|
|
OS << "extern const char " << TargetName << "RegStrings[];\n";
|
|
OS << "extern const char " << TargetName << "RegClassStrings[];\n";
|
|
OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
|
|
OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
|
|
OS << "extern const MCRegisterInfo::SubRegCoveredBits "
|
|
<< TargetName << "SubRegIdxRanges[];\n";
|
|
OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
|
|
|
|
EmitRegMappingTables(OS, Regs, true);
|
|
|
|
OS << ClassName << "::\n" << ClassName
|
|
<< "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
|
|
<< " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
|
|
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
|
|
<< " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x";
|
|
OS.write_hex(RegBank.CoveringLanes);
|
|
OS << ") {\n"
|
|
<< " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
|
|
<< ", RA, PC,\n " << TargetName
|
|
<< "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
|
|
<< " " << TargetName << "RegUnitRoots,\n"
|
|
<< " " << RegBank.getNumNativeRegUnits() << ",\n"
|
|
<< " " << TargetName << "RegDiffLists,\n"
|
|
<< " " << TargetName << "LaneMaskLists,\n"
|
|
<< " " << TargetName << "RegStrings,\n"
|
|
<< " " << TargetName << "RegClassStrings,\n"
|
|
<< " " << TargetName << "SubRegIdxLists,\n"
|
|
<< " " << SubRegIndicesSize + 1 << ",\n"
|
|
<< " " << TargetName << "SubRegIdxRanges,\n"
|
|
<< " " << TargetName << "RegEncodingTable);\n\n";
|
|
|
|
EmitRegMapping(OS, Regs, true);
|
|
|
|
OS << "}\n\n";
|
|
|
|
|
|
// Emit CalleeSavedRegs information.
|
|
std::vector<Record*> CSRSets =
|
|
Records.getAllDerivedDefinitions("CalleeSavedRegs");
|
|
for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
|
|
Record *CSRSet = CSRSets[i];
|
|
const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
|
|
assert(Regs && "Cannot expand CalleeSavedRegs instance");
|
|
|
|
// Emit the *_SaveList list of callee-saved registers.
|
|
OS << "static const MCPhysReg " << CSRSet->getName()
|
|
<< "_SaveList[] = { ";
|
|
for (unsigned r = 0, re = Regs->size(); r != re; ++r)
|
|
OS << getQualifiedName((*Regs)[r]) << ", ";
|
|
OS << "0 };\n";
|
|
|
|
// Emit the *_RegMask bit mask of call-preserved registers.
|
|
BitVector Covered = RegBank.computeCoveredRegisters(*Regs);
|
|
|
|
// Check for an optional OtherPreserved set.
|
|
// Add those registers to RegMask, but not to SaveList.
|
|
if (DagInit *OPDag =
|
|
dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) {
|
|
SetTheory::RecSet OPSet;
|
|
RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
|
|
Covered |= RegBank.computeCoveredRegisters(
|
|
ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
|
|
}
|
|
|
|
OS << "static const uint32_t " << CSRSet->getName()
|
|
<< "_RegMask[] = { ";
|
|
printBitVectorAsHex(OS, Covered, 32);
|
|
OS << "};\n";
|
|
}
|
|
OS << "\n\n";
|
|
|
|
OS << "} // End llvm namespace\n";
|
|
OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
|
|
}
|
|
|
|
void RegisterInfoEmitter::run(raw_ostream &OS) {
|
|
CodeGenTarget Target(Records);
|
|
CodeGenRegBank &RegBank = Target.getRegBank();
|
|
RegBank.computeDerivedInfo();
|
|
|
|
runEnums(OS, Target, RegBank);
|
|
runMCDesc(OS, Target, RegBank);
|
|
runTargetHeader(OS, Target, RegBank);
|
|
runTargetDesc(OS, Target, RegBank);
|
|
}
|
|
|
|
namespace llvm {
|
|
|
|
void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
|
|
RegisterInfoEmitter(RK).run(OS);
|
|
}
|
|
|
|
} // End llvm namespace
|