Ruslan Bukin 9862cef040 o Separate rtc and timecmp registers: they are different across ... RISC-V cpu implementations. o Update RocketChip device tree source (DTS). We now support latest verison of RocketChip synthesized on Xilinx FPGA (Zedboard). RocketChip is an implementation of RISC-V processor written on Chisel hardware construction language. Sponsored by: DARPA, AFRL Sponsored by: HEIF5		2016-09-01 14:58:11 +00:00
..
arm	Remove pullup settings for MMC pins, this is not needed since r304290	2016-08-17 13:19:28 +00:00
arm64	Add Allwinner A64 (sun50i) and Pine64 dts files.	2016-08-31 16:56:54 +00:00
mips	Add proper PCIe init for MT7628/MT7688 SoCs	2016-05-17 06:45:25 +00:00
powerpc	Mov p2041rdb.dts, p3041ds.dts, and p5020ds.dts to the powerpc directory.	2014-06-07 02:55:53 +00:00
riscv	o Separate rtc and timecmp registers: they are different across	2016-09-01 14:58:11 +00:00
bindings-gpio.txt	Add the missing ')' at end of sentence. Reword it to use a more common	2014-02-05 17:08:55 +00:00
bindings-localbus.txt	Add architecture dependent code to support NAND Framework on Marvell SoCs.	2012-05-18 14:41:14 +00:00
bindings-mpp.txt
Makefile	Add Allwinner A64 (sun50i) and Pine64 dts files.	2016-08-31 16:56:54 +00:00
Makefile.inc	Fix the script to run make_dtb.sh instead of just dtc.	2014-06-07 02:38:13 +00:00