405 lines
8.5 KiB
C
405 lines
8.5 KiB
C
/*-
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* Copyright 1996 Massachusetts Institute of Technology
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby
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* granted, provided that both the above copyright notice and this
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* permission notice appear in all copies, that both the above
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* copyright notice and this permission notice appear in all
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* supporting documentation, and that the name of M.I.T. not be used
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* in advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission. M.I.T. makes
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* no representations about the suitability of this software for any
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* purpose. It is provided "as is" without express or implied
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* warranty.
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*
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* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
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* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
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* SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/fcntl.h>
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#include <sys/kernel.h>
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#ifndef SMP
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#include <machine/cputypes.h>
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#endif
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#include <machine/clock.h>
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#include <machine/perfmon.h>
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#include <machine/specialreg.h>
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static int perfmon_inuse;
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static int perfmon_cpuok;
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#ifndef SMP
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static int msr_ctl[NPMC];
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#endif
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static int msr_pmc[NPMC];
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static unsigned int ctl_shadow[NPMC];
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static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
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static int (*writectl)(int);
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#ifndef SMP
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static int writectl5(int);
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static int writectl6(int);
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#endif
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static d_close_t perfmon_close;
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static d_open_t perfmon_open;
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static d_ioctl_t perfmon_ioctl;
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/*
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* XXX perfmon_init_dev(void *) is a split from the perfmon_init() funtion.
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* This solves a problem for DEVFS users. It loads the "perfmon" driver after
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* the DEVFS subsystem has been kicked into action. The SI_ORDER_ANY is to
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* assure that it is the most lowest priority task which, guarantees the
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* above.
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*/
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static void perfmon_init_dev(void *);
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SYSINIT(cpu, SI_SUB_DRIVERS, SI_ORDER_ANY, perfmon_init_dev, NULL);
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static struct cdevsw perfmon_cdevsw = {
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.d_version = D_VERSION,
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.d_flags = D_NEEDGIANT,
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.d_open = perfmon_open,
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.d_close = perfmon_close,
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.d_ioctl = perfmon_ioctl,
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.d_name = "perfmon",
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};
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/*
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* Must be called after cpu_class is set up.
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*/
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void
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perfmon_init(void)
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{
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#ifndef SMP
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switch(cpu_class) {
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case CPUCLASS_586:
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perfmon_cpuok = 1;
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msr_ctl[0] = MSR_P5_CESR;
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msr_ctl[1] = MSR_P5_CESR;
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msr_pmc[0] = MSR_P5_CTR0;
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msr_pmc[1] = MSR_P5_CTR1;
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writectl = writectl5;
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break;
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case CPUCLASS_686:
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perfmon_cpuok = 1;
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msr_ctl[0] = MSR_EVNTSEL0;
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msr_ctl[1] = MSR_EVNTSEL1;
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msr_pmc[0] = MSR_PERFCTR0;
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msr_pmc[1] = MSR_PERFCTR1;
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writectl = writectl6;
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break;
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default:
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perfmon_cpuok = 0;
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break;
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}
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#endif /* SMP */
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}
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static void
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perfmon_init_dev(dummy)
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void *dummy;
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{
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make_dev(&perfmon_cdevsw, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
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}
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int
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perfmon_avail(void)
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{
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return perfmon_cpuok;
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}
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int
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perfmon_setup(int pmc, unsigned int control)
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{
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register_t savecrit;
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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perfmon_inuse |= (1 << pmc);
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control &= ~(PMCF_SYS_FLAGS << 16);
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savecrit = intr_disable();
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ctl_shadow[pmc] = control;
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writectl(pmc);
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wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
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intr_restore(savecrit);
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return 0;
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}
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int
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perfmon_get(int pmc, unsigned int *control)
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{
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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*control = ctl_shadow[pmc];
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return 0;
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}
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return EBUSY; /* XXX reversed sense */
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}
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int
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perfmon_fini(int pmc)
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{
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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perfmon_stop(pmc);
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ctl_shadow[pmc] = 0;
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perfmon_inuse &= ~(1 << pmc);
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return 0;
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}
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return EBUSY; /* XXX reversed sense */
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}
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int
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perfmon_start(int pmc)
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{
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register_t savecrit;
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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savecrit = intr_disable();
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ctl_shadow[pmc] |= (PMCF_EN << 16);
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wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
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writectl(pmc);
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intr_restore(savecrit);
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return 0;
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}
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return EBUSY;
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}
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int
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perfmon_stop(int pmc)
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{
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register_t savecrit;
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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savecrit = intr_disable();
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pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
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ctl_shadow[pmc] &= ~(PMCF_EN << 16);
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writectl(pmc);
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intr_restore(savecrit);
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return 0;
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}
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return EBUSY;
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}
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int
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perfmon_read(int pmc, quad_t *val)
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{
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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if (ctl_shadow[pmc] & (PMCF_EN << 16))
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*val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
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else
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*val = pmc_shadow[pmc];
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return 0;
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}
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return EBUSY;
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}
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int
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perfmon_reset(int pmc)
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{
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
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return 0;
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}
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return EBUSY;
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}
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#ifndef SMP
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/*
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* Unfortunately, the performance-monitoring registers are laid out
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* differently in the P5 and P6. We keep everything in P6 format
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* internally (except for the event code), and convert to P5
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* format as needed on those CPUs. The writectl function pointer
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* is set up to point to one of these functions by perfmon_init().
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*/
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int
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writectl6(int pmc)
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{
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if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
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wrmsr(msr_ctl[pmc], 0);
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} else {
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wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
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}
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return 0;
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}
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#define P5FLAG_P 0x200
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#define P5FLAG_E 0x100
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#define P5FLAG_USR 0x80
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#define P5FLAG_OS 0x40
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int
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writectl5(int pmc)
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{
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quad_t newval = 0;
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if (ctl_shadow[1] & (PMCF_EN << 16)) {
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if (ctl_shadow[1] & (PMCF_USR << 16))
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newval |= P5FLAG_USR << 16;
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if (ctl_shadow[1] & (PMCF_OS << 16))
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newval |= P5FLAG_OS << 16;
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if (!(ctl_shadow[1] & (PMCF_E << 16)))
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newval |= P5FLAG_E << 16;
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newval |= (ctl_shadow[1] & 0x3f) << 16;
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}
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if (ctl_shadow[0] & (PMCF_EN << 16)) {
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if (ctl_shadow[0] & (PMCF_USR << 16))
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newval |= P5FLAG_USR;
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if (ctl_shadow[0] & (PMCF_OS << 16))
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newval |= P5FLAG_OS;
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if (!(ctl_shadow[0] & (PMCF_E << 16)))
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newval |= P5FLAG_E;
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newval |= ctl_shadow[0] & 0x3f;
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}
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wrmsr(msr_ctl[0], newval);
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return 0; /* XXX should check for unimplemented bits */
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}
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#endif /* !SMP */
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/*
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* Now the user-mode interface, called from a subdevice of mem.c.
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*/
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static int writer;
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static int writerpmc;
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static int
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perfmon_open(struct cdev *dev, int flags, int fmt, struct thread *td)
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{
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if (!perfmon_cpuok)
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return ENXIO;
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if (flags & FWRITE) {
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if (writer) {
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return EBUSY;
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} else {
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writer = 1;
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writerpmc = 0;
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}
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}
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return 0;
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}
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static int
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perfmon_close(struct cdev *dev, int flags, int fmt, struct thread *td)
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{
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if (flags & FWRITE) {
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int i;
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for (i = 0; i < NPMC; i++) {
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if (writerpmc & (1 << i))
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perfmon_fini(i);
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}
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writer = 0;
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}
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return 0;
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}
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static int
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perfmon_ioctl(struct cdev *dev, u_long cmd, caddr_t param, int flags, struct thread *td)
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{
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struct pmc *pmc;
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struct pmc_data *pmcd;
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struct pmc_tstamp *pmct;
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int *ip;
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int rv;
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switch(cmd) {
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case PMIOSETUP:
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if (!(flags & FWRITE))
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return EPERM;
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pmc = (struct pmc *)param;
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rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
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if (!rv) {
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writerpmc |= (1 << pmc->pmc_num);
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}
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break;
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case PMIOGET:
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pmc = (struct pmc *)param;
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rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
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break;
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case PMIOSTART:
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if (!(flags & FWRITE))
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return EPERM;
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ip = (int *)param;
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rv = perfmon_start(*ip);
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break;
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case PMIOSTOP:
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if (!(flags & FWRITE))
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return EPERM;
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ip = (int *)param;
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rv = perfmon_stop(*ip);
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break;
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case PMIORESET:
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if (!(flags & FWRITE))
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return EPERM;
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ip = (int *)param;
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rv = perfmon_reset(*ip);
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break;
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case PMIOREAD:
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pmcd = (struct pmc_data *)param;
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rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
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break;
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case PMIOTSTAMP:
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if (!tsc_freq) {
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rv = ENOTTY;
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break;
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}
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pmct = (struct pmc_tstamp *)param;
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/* XXX interface loses precision. */
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pmct->pmct_rate = tsc_freq / 1000000;
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pmct->pmct_value = rdtsc();
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rv = 0;
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break;
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default:
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rv = ENOTTY;
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}
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return rv;
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}
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