340 lines
14 KiB
C++
340 lines
14 KiB
C++
//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include <vector>
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namespace llvm {
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/// MachineRegisterInfo - Keep track of information for virtual and physical
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/// registers, including vreg register classes, use/def chains for registers,
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/// etc.
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class MachineRegisterInfo {
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/// VRegInfo - Information we keep for each virtual register. The entries in
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/// this vector are actually converted to vreg numbers by adding the
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/// TargetRegisterInfo::FirstVirtualRegister delta to their index.
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///
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/// Each element in this list contains the register class of the vreg and the
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/// start of the use/def list for the register.
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std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
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/// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
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/// virtual registers. For each target register class, it keeps a list of
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/// virtual registers belonging to the class.
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std::vector<std::vector<unsigned> > RegClass2VRegMap;
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/// RegAllocHints - This vector records register allocation hints for virtual
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/// registers. For each virtual register, it keeps a register and hint type
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/// pair making up the allocation hint. Hint type is target specific except
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/// for the value 0 which means the second value of the pair is the preferred
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/// register for allocation. For example, if the hint is <0, 1024>, it means
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/// the allocator should prefer the physical register allocated to the virtual
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/// register of the hint.
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std::vector<std::pair<unsigned, unsigned> > RegAllocHints;
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/// PhysRegUseDefLists - This is an array of the head of the use/def list for
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/// physical registers.
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MachineOperand **PhysRegUseDefLists;
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/// UsedPhysRegs - This is a bit vector that is computed and set by the
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/// register allocator, and must be kept up to date by passes that run after
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/// register allocation (though most don't modify this). This is used
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/// so that the code generator knows which callee save registers to save and
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/// for other target specific uses.
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BitVector UsedPhysRegs;
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/// LiveIns/LiveOuts - Keep track of the physical registers that are
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/// livein/liveout of the function. Live in values are typically arguments in
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/// registers, live out values are typically return values in registers.
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/// LiveIn values are allowed to have virtual registers associated with them,
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/// stored in the second element.
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std::vector<std::pair<unsigned, unsigned> > LiveIns;
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std::vector<unsigned> LiveOuts;
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MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
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void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
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public:
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explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
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~MachineRegisterInfo();
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//===--------------------------------------------------------------------===//
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// Register Info
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//===--------------------------------------------------------------------===//
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/// reg_begin/reg_end - Provide iteration support to walk over all definitions
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/// and uses of a register within the MachineFunction that corresponds to this
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/// MachineRegisterInfo object.
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template<bool Uses, bool Defs>
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class defusechain_iterator;
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/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
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/// register.
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typedef defusechain_iterator<true,true> reg_iterator;
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reg_iterator reg_begin(unsigned RegNo) const {
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return reg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_iterator reg_end() { return reg_iterator(0); }
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/// reg_empty - Return true if there are no instructions using or defining the
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/// specified register (it may be live-in).
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bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
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/// def_iterator/def_begin/def_end - Walk all defs of the specified register.
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typedef defusechain_iterator<false,true> def_iterator;
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def_iterator def_begin(unsigned RegNo) const {
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return def_iterator(getRegUseDefListHead(RegNo));
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}
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static def_iterator def_end() { return def_iterator(0); }
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/// def_empty - Return true if there are no instructions defining the
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/// specified register (it may be live-in).
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bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
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/// use_iterator/use_begin/use_end - Walk all uses of the specified register.
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typedef defusechain_iterator<true,false> use_iterator;
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use_iterator use_begin(unsigned RegNo) const {
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return use_iterator(getRegUseDefListHead(RegNo));
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}
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static use_iterator use_end() { return use_iterator(0); }
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/// use_empty - Return true if there are no instructions using the specified
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/// register.
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bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
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/// replaceRegWith - Replace all instances of FromReg with ToReg in the
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/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
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/// except that it also changes any definitions of the register as well.
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void replaceRegWith(unsigned FromReg, unsigned ToReg);
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/// getRegUseDefListHead - Return the head pointer for the register use/def
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/// list for the specified virtual or physical register.
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MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
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if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
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return PhysRegUseDefLists[RegNo];
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RegNo -= TargetRegisterInfo::FirstVirtualRegister;
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return VRegInfo[RegNo].second;
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}
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MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
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if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
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return PhysRegUseDefLists[RegNo];
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RegNo -= TargetRegisterInfo::FirstVirtualRegister;
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return VRegInfo[RegNo].second;
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}
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/// getVRegDef - Return the machine instr that defines the specified virtual
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/// register or null if none is found. This assumes that the code is in SSA
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/// form, so there should only be one definition.
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MachineInstr *getVRegDef(unsigned Reg) const;
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#ifndef NDEBUG
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void dumpUses(unsigned RegNo) const;
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#endif
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//===--------------------------------------------------------------------===//
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// Virtual Register Info
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//===--------------------------------------------------------------------===//
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/// getRegClass - Return the register class of the specified virtual register.
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///
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const TargetRegisterClass *getRegClass(unsigned Reg) const {
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Reg -= TargetRegisterInfo::FirstVirtualRegister;
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assert(Reg < VRegInfo.size() && "Invalid vreg!");
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return VRegInfo[Reg].first;
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}
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/// setRegClass - Set the register class of the specified virtual register.
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///
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void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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///
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unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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/// getLastVirtReg - Return the highest currently assigned virtual register.
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///
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unsigned getLastVirtReg() const {
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return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
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}
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/// getRegClassVirtRegs - Return the list of virtual registers of the given
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/// target register class.
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std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
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return RegClass2VRegMap[RC->getID()];
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}
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/// setRegAllocationHint - Specify a register allocation hint for the
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/// specified virtual register.
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void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
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Reg -= TargetRegisterInfo::FirstVirtualRegister;
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assert(Reg < VRegInfo.size() && "Invalid vreg!");
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RegAllocHints[Reg].first = Type;
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RegAllocHints[Reg].second = PrefReg;
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}
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/// getRegAllocationHint - Return the register allocation hint for the
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/// specified virtual register.
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std::pair<unsigned, unsigned>
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getRegAllocationHint(unsigned Reg) const {
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Reg -= TargetRegisterInfo::FirstVirtualRegister;
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assert(Reg < VRegInfo.size() && "Invalid vreg!");
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return RegAllocHints[Reg];
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}
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//===--------------------------------------------------------------------===//
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// Physical Register Use Info
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//===--------------------------------------------------------------------===//
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/// isPhysRegUsed - Return true if the specified register is used in this
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/// function. This only works after register allocation.
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bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
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/// setPhysRegUsed - Mark the specified register used in this function.
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/// This should only be called during and after register allocation.
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void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
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/// setPhysRegUnused - Mark the specified register unused in this function.
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/// This should only be called during and after register allocation.
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void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
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//===--------------------------------------------------------------------===//
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// LiveIn/LiveOut Management
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//===--------------------------------------------------------------------===//
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/// addLiveIn/Out - Add the specified register as a live in/out. Note that it
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/// is an error to add the same register to the same set more than once.
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void addLiveIn(unsigned Reg, unsigned vreg = 0) {
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LiveIns.push_back(std::make_pair(Reg, vreg));
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}
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void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
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// Iteration support for live in/out sets. These sets are kept in sorted
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// order by their register number.
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typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
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livein_iterator;
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typedef std::vector<unsigned>::const_iterator liveout_iterator;
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livein_iterator livein_begin() const { return LiveIns.begin(); }
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livein_iterator livein_end() const { return LiveIns.end(); }
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bool livein_empty() const { return LiveIns.empty(); }
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liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
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liveout_iterator liveout_end() const { return LiveOuts.end(); }
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bool liveout_empty() const { return LiveOuts.empty(); }
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bool isLiveIn(unsigned Reg) const {
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for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
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if (I->first == Reg || I->second == Reg)
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return true;
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return false;
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}
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bool isLiveOut(unsigned Reg) const {
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for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
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if (*I == Reg)
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return true;
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return false;
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}
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private:
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void HandleVRegListReallocation();
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public:
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/// defusechain_iterator - This class provides iterator support for machine
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/// operands in the function that use or define a specific register. If
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/// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
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/// returns defs. If neither are true then you are silly and it always
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/// returns end().
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template<bool ReturnUses, bool ReturnDefs>
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class defusechain_iterator
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: public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
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MachineOperand *Op;
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explicit defusechain_iterator(MachineOperand *op) : Op(op) {
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// If the first node isn't one we're interested in, advance to one that
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// we are interested in.
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if (op) {
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if ((!ReturnUses && op->isUse()) ||
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(!ReturnDefs && op->isDef()))
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++*this;
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}
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}
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friend class MachineRegisterInfo;
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public:
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typedef std::iterator<std::forward_iterator_tag,
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MachineInstr, ptrdiff_t>::reference reference;
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typedef std::iterator<std::forward_iterator_tag,
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MachineInstr, ptrdiff_t>::pointer pointer;
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defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
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defusechain_iterator() : Op(0) {}
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bool operator==(const defusechain_iterator &x) const {
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return Op == x.Op;
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}
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bool operator!=(const defusechain_iterator &x) const {
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return !operator==(x);
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}
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/// atEnd - return true if this iterator is equal to reg_end() on the value.
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bool atEnd() const { return Op == 0; }
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// Iterator traversal: forward iteration only
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defusechain_iterator &operator++() { // Preincrement
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assert(Op && "Cannot increment end iterator!");
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Op = Op->getNextOperandForReg();
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// If this is an operand we don't care about, skip it.
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while (Op && ((!ReturnUses && Op->isUse()) ||
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(!ReturnDefs && Op->isDef())))
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Op = Op->getNextOperandForReg();
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return *this;
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}
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defusechain_iterator operator++(int) { // Postincrement
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defusechain_iterator tmp = *this; ++*this; return tmp;
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}
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MachineOperand &getOperand() const {
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assert(Op && "Cannot dereference end iterator!");
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return *Op;
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}
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/// getOperandNo - Return the operand # of this MachineOperand in its
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/// MachineInstr.
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unsigned getOperandNo() const {
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assert(Op && "Cannot dereference end iterator!");
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return Op - &Op->getParent()->getOperand(0);
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}
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// Retrieve a reference to the current operand.
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MachineInstr &operator*() const {
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assert(Op && "Cannot dereference end iterator!");
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return *Op->getParent();
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}
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MachineInstr *operator->() const {
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assert(Op && "Cannot dereference end iterator!");
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return Op->getParent();
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}
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};
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};
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} // End llvm namespace
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#endif
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