611f086953
In n32 and n64, add support for physical address above 4GB by having 64 bit page table entries and physical addresses. Major changes are: - param.h: update PTE sizes, masks and shift values to support 64 bit PTEs. - param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as ptoa), and reformat. - param.h: remove casting to unsigned long in trunc_page and round_page since this will be used on physical addresses. - _types.h: have 64 bit __vm_paddr_t for n32. - pte.h: update TLB LO0/1 access macros to support 64 bit PTE - pte.h: assembly macros for PTE operations. - proc.h: md_upte is now 64 bit for n32 and n64. - exception.S and swtch.S: use the new PTE macros for PTE operations. - cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64. - xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are supported now. Reviewed by: jmallett (earlier version)
176 lines
6.4 KiB
C
176 lines
6.4 KiB
C
/*-
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* Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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#ifndef _LOCORE
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#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
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typedef uint64_t pt_entry_t;
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#else
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typedef uint32_t pt_entry_t;
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#endif
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typedef pt_entry_t *pd_entry_t;
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#endif
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/*
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* TLB and PTE management. Most things operate within the context of
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* EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi
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* start with TLBHI_. PTE bits begin with PTE_.
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*
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* Note that we use the same size VM and TLB pages.
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*/
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#define TLB_PAGE_SHIFT (PAGE_SHIFT)
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#define TLB_PAGE_SIZE (1 << TLB_PAGE_SHIFT)
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#define TLB_PAGE_MASK (TLB_PAGE_SIZE - 1)
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/*
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* TLB PageMask register. Has mask bits set above the default, 4K, page mask.
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*/
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#define TLBMASK_SHIFT (13)
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#define TLBMASK_MASK ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT)
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/*
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* PFN for EntryLo register. Upper bits are 0, which is to say that
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* bit 29 is the last hardware bit; Bits 30 and upwards (EntryLo is
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* 64 bit though it can be referred to in 32-bits providing 2 software
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* bits safely. We use it as 64 bits to get many software bits, and
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* god knows what else.) are unacknowledged by hardware. They may be
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* written as anything, but otherwise they have as much meaning as
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* other 0 fields.
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*/
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#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
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#define TLBLO_SWBITS_SHIFT (34)
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#define TLBLO_PFN_MASK 0x3FFFFFFC0ULL
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#else
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#define TLBLO_SWBITS_SHIFT (30)
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#define TLBLO_PFN_MASK (0x3FFFFFC0)
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#endif
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#define TLBLO_PFN_SHIFT (6)
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#define TLBLO_SWBITS_MASK ((pt_entry_t)0x3 << TLBLO_SWBITS_SHIFT)
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#define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK)
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#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
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#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK)
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#define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte))))
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/*
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* XXX This comment is not correct for anything more modern than R4K.
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*
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* VPN for EntryHi register. Upper two bits select user, supervisor,
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* or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to
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* as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12
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* to bit 8 there is a 5-bit 0 field. Low byte is ASID.
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*
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* XXX This comment is not correct for FreeBSD.
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* Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
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*/
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#define TLBHI_ASID_MASK (0xff)
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#if defined(__mips_n64)
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#define TLBHI_R_SHIFT 62
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#define TLBHI_R_USER (0x00UL << TLBHI_R_SHIFT)
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#define TLBHI_R_SUPERVISOR (0x01UL << TLBHI_R_SHIFT)
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#define TLBHI_R_KERNEL (0x03UL << TLBHI_R_SHIFT)
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#define TLBHI_R_MASK (0x03UL << TLBHI_R_SHIFT)
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#define TLBHI_VA_R(va) ((va) & TLBHI_R_MASK)
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#define TLBHI_FILL_SHIFT 40
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#define TLBHI_VPN2_SHIFT (TLB_PAGE_SHIFT + 1)
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#define TLBHI_VPN2_MASK (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT))
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#define TLBHI_VA_TO_VPN2(va) ((va) & TLBHI_VPN2_MASK)
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#define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \
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(TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \
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((asid) & TLBHI_ASID_MASK))
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#else /* !defined(__mips_n64) */
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#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1)
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#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
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#endif /* defined(__mips_n64) */
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/*
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* TLB flags managed in hardware:
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* C: Cache attribute.
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* D: Dirty bit. This means a page is writable. It is not
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* set at first, and a write is trapped, and the dirty
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* bit is set. See also PTE_RO.
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* V: Valid bit. Obvious, isn't it?
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* G: Global bit. This means that this mapping is present
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* in EVERY address space, and to ignore the ASID when
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* it is matched.
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*/
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#define PTE_C(attr) ((attr & 0x07) << 3)
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#define PTE_C_UNCACHED (PTE_C(MIPS_CCA_UNCACHED))
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#define PTE_C_CACHE (PTE_C(MIPS_CCA_CACHED))
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#define PTE_D 0x04
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#define PTE_V 0x02
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#define PTE_G 0x01
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/*
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* VM flags managed in software:
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* RO: Read only. Never set PTE_D on this page, and don't
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* listen to requests to write to it.
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* W: Wired. ???
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*/
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#define PTE_RO ((pt_entry_t)0x01 << TLBLO_SWBITS_SHIFT)
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#define PTE_W ((pt_entry_t)0x02 << TLBLO_SWBITS_SHIFT)
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/*
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* PTE management functions for bits defined above.
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*/
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#define pte_clear(pte, bit) (*(pte) &= ~(bit))
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#define pte_set(pte, bit) (*(pte) |= (bit))
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#define pte_test(pte, bit) ((*(pte) & (bit)) == (bit))
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/* Assembly support for PTE access*/
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#ifdef LOCORE
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#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
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#define PTESHIFT 3
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#define PTE2MASK 0xff0 /* for the 2-page lo0/lo1 */
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#define PTEMASK 0xff8
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#define PTESIZE 8
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#define PTE_L ld
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#define PTE_MTC0 dmtc0
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#define CLEAR_PTE_SWBITS(pr)
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#else
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#define PTESHIFT 2
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#define PTE2MASK 0xff8 /* for the 2-page lo0/lo1 */
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#define PTEMASK 0xffc
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#define PTESIZE 4
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#define PTE_L lw
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#define PTE_MTC0 mtc0
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#define CLEAR_PTE_SWBITS(r) sll r, 2; srl r, 2 /* remove 2 high bits */
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#endif /* defined(__mips_n64) || defined(__mips_n32) */
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#if defined(__mips_n64)
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#define PTRSHIFT 3
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#define PDEPTRMASK 0xff8
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#else
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#define PTRSHIFT 2
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#define PDEPTRMASK 0xffc
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#endif
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#endif /* LOCORE */
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#endif /* !_MACHINE_PTE_H_ */
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