98f9879242
and it's associated state variables: icu_lock with the name "icu". This renames the imen_mtx for x86 SMP, but also uses the lock to protect access to the 8259 PIC on x86 UP. This also adds an appropriate lock to the various Alpha chipsets which fixes problems with Alpha SMP machines dropping interrupts with an SMP kernel.
412 lines
9.4 KiB
C
412 lines
9.4 KiB
C
/*-
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* Copyright (c) 1999 Andrew Gallatin
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/interrupt.h>
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#include <sys/malloc.h>
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#include <pci/pcivar.h>
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#include <alpha/isa/isavar.h>
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#include <alpha/pci/tsunamireg.h>
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#include <alpha/pci/tsunamivar.h>
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#include <machine/bwx.h>
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#include <machine/intr.h>
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#include <machine/intrcnt.h>
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#include <machine/cpuconf.h>
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#include <machine/rpb.h>
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#include <machine/resource.h>
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#include <machine/sgmap.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t tsunami_devclass;
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static device_t tsunami0; /* XXX only one for now */
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struct tsunami_softc {
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int junk; /* no softc */
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};
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int tsunami_num_pchips = 0;
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static volatile tsunami_pchip *pchip[2] = {pchip0, pchip1};
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#define TSUNAMI_SOFTC(dev) (struct tsunami_softc*) device_get_softc(dev)
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static alpha_chipset_read_hae_t tsunami_read_hae;
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static alpha_chipset_write_hae_t tsunami_write_hae;
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static alpha_chipset_t tsunami_chipset = {
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tsunami_read_hae,
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tsunami_write_hae,
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};
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static void tsunami_intr_enable __P((int));
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static void tsunami_intr_disable __P((int));
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/*
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* There doesn't appear to be an hae on this platform
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*/
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static u_int64_t
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tsunami_read_hae(void)
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{
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return 0;
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}
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static void
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tsunami_write_hae(u_int64_t hae)
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{
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}
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static int tsunami_probe(device_t dev);
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static int tsunami_attach(device_t dev);
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static int tsunami_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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driver_intr_t *intr, void *arg, void **cookiep);
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static int tsunami_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie);
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static device_method_t tsunami_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, tsunami_probe),
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DEVMETHOD(device_attach, tsunami_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_setup_intr, tsunami_setup_intr),
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DEVMETHOD(bus_teardown_intr, tsunami_teardown_intr),
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{ 0, 0 }
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};
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static driver_t tsunami_driver = {
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"tsunami",
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tsunami_methods,
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sizeof(struct tsunami_softc),
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};
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static void
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pchip_init(volatile tsunami_pchip *pchip, int index)
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{
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int i;
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/*
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* initialize the direct map DMA windows.
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*
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* leave window 0 untouched; we'll set that up for S/G DMA for
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* isa devices later in the boot process
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*
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* window 1 goes at 2GB and has a length of 1 GB. It maps
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* physical address 0 - 1GB. The SRM console typically sets
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* this window up here.
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*/
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pchip->wsba[1].reg = (2UL*1024*1024*1024) | WINDOW_ENABLE;
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pchip->wsm[1].reg = (1UL*1024*1024*1024 - 1) & 0xfff00000UL;
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pchip->tba[1].reg = 0;
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/*
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* window 2 goes at 3GB and has a length of 1 GB. It maps
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* physical address 1GB-2GB.
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*/
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pchip->wsba[2].reg = (3UL*1024*1024*1024) | WINDOW_ENABLE;
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pchip->wsm[2].reg = (1UL*1024*1024*1024 - 1) & 0xfff00000UL;
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pchip->tba[2].reg = 1UL*1024*1024*1024;
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/*
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* window 3 is disabled. The SRM console typically leaves it
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* disabled
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*/
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pchip->wsba[3].reg = 0;
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alpha_mb();
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if(bootverbose) {
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printf("pchip%d:\n", index);
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for (i = 0; i < 4; i++) {
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printf("\twsba[%d].reg = 0x%lx\n",
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i, pchip->wsba[i].reg);
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printf("\t wsm[%d].reg = 0x%lx\n",
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i, pchip->wsm[i].reg);
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printf("\t tba[%d].reg = 0x%lx\n",
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i, pchip->tba[i].reg);
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}
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}
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}
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#define TSUNAMI_SGMAP_BASE (8*1024*1024)
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#define TSUNAMI_SGMAP_SIZE (8*1024*1024)
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static void
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tsunami_sgmap_invalidate(void)
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{
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alpha_mb();
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switch (tsunami_num_pchips) {
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case 2:
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pchip[1]->tlbia.reg = (u_int64_t)0;
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case 1:
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pchip[0]->tlbia.reg = (u_int64_t)0;
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}
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alpha_mb();
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}
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static void
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tsunami_sgmap_map(void *arg, bus_addr_t ba, vm_offset_t pa)
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{
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u_int64_t *sgtable = arg;
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int index = alpha_btop(ba - TSUNAMI_SGMAP_BASE);
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if (pa) {
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if (pa > (1L<<32))
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panic("tsunami_sgmap_map: can't map address 0x%lx", pa);
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sgtable[index] = ((pa >> 13) << 1) | 1;
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} else {
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sgtable[index] = 0;
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}
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alpha_mb();
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tsunami_sgmap_invalidate();
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}
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static void
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tsunami_init_sgmap(void)
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{
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void *sgtable;
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int i;
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sgtable = contigmalloc(8192, M_DEVBUF, M_NOWAIT,
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0, (1L<<34),
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32*1024, (1L<<34));
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if (!sgtable)
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panic("tsunami_init_sgmap: can't allocate page table");
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for(i=0; i < tsunami_num_pchips; i++){
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pchip[i]->tba[0].reg =
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pmap_kextract((vm_offset_t) sgtable);
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pchip[i]->wsba[0].reg |= WINDOW_ENABLE | WINDOW_SCATTER_GATHER;
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}
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chipset.sgmap = sgmap_map_create(TSUNAMI_SGMAP_BASE,
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TSUNAMI_SGMAP_BASE + TSUNAMI_SGMAP_SIZE,
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tsunami_sgmap_map, sgtable);
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}
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void
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tsunami_init()
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{
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static int initted = 0;
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static struct bwx_space io_space;
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static struct bwx_space mem_space;
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if (initted) return;
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initted = 1;
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/*
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* Define two temporary spaces for bootstrap i/o on hose 0.
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*/
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bwx_init_space(&io_space, KV(TSUNAMI_IO(0)));
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bwx_init_space(&mem_space, KV(TSUNAMI_MEM(0)));
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busspace_isa_io = (struct alpha_busspace *) &io_space;
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busspace_isa_mem = (struct alpha_busspace *) &mem_space;
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chipset = tsunami_chipset;
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platform.pci_intr_enable = tsunami_intr_enable;
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platform.pci_intr_disable = tsunami_intr_disable;
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alpha_XXX_dmamap_or = 2UL * 1024UL * 1024UL * 1024UL;
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if (platform.pci_intr_init)
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platform.pci_intr_init();
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}
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static int
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tsunami_probe(device_t dev)
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{
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device_t child;
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int i;
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if (tsunami0)
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return ENXIO;
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tsunami0 = dev;
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device_set_desc(dev, "21271 Core Logic chipset");
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if(cchip->csc.reg & CSC_P1P)
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tsunami_num_pchips = 2;
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else
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tsunami_num_pchips = 1;
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isa_init_intr();
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for(i = 0; i < tsunami_num_pchips; i++) {
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child = device_add_child(dev, "pcib", i);
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pchip_init(pchip[i], i);
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}
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return 0;
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}
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static int
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tsunami_attach(device_t dev)
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{
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tsunami_init();
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if (!platform.iointr) /* XXX */
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set_iointr(alpha_dispatch_intr);
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snprintf(chipset_type, sizeof(chipset_type), "tsunami");
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chipset_bwx = 1;
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chipset_ports = TSUNAMI_IO(0);
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chipset_memory = TSUNAMI_MEM(0);
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chipset_dense = TSUNAMI_MEM(0);
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bus_generic_attach(dev);
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tsunami_init_sgmap();
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return 0;
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}
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static void
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tsunami_disable_intr_vec(int vector)
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{
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int irq;
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irq = (vector - 0x900) >> 4;
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mtx_lock_spin(&icu_lock);
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platform.pci_intr_disable(irq);
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mtx_unlock_spin(&icu_lock);
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}
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static void
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tsunami_enable_intr_vec(int vector)
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{
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int irq;
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irq = (vector - 0x900) >> 4;
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mtx_lock_spin(&icu_lock);
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platform.pci_intr_enable(irq);
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mtx_unlock_spin(&icu_lock);
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}
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static int
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tsunami_setup_intr(device_t dev, device_t child,
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struct resource *irq, int flags,
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driver_intr_t *intr, void *arg, void **cookiep)
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{
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int error;
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error = rman_activate_resource(irq);
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if (error)
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return error;
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error = alpha_setup_intr(device_get_nameunit(child ? child : dev),
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0x900 + (irq->r_start << 4), intr, arg, flags, cookiep,
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&intrcnt[INTRCNT_EB164_IRQ + irq->r_start],
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tsunami_disable_intr_vec, tsunami_enable_intr_vec);
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if (error)
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return error;
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/* Enable PCI interrupt */
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mtx_lock_spin(&icu_lock);
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platform.pci_intr_enable(irq->r_start);
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mtx_unlock_spin(&icu_lock);
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device_printf(child, "interrupting at TSUNAMI irq %d\n",
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(int) irq->r_start);
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return 0;
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}
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static int
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tsunami_teardown_intr(device_t dev, device_t child,
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struct resource *irq, void *cookie)
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{
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alpha_teardown_intr(cookie);
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return rman_deactivate_resource(irq);
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}
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/*
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* Currently, all interrupts will be funneled through CPU 0
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*/
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static void
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tsunami_intr_enable(int irq)
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{
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volatile u_int64_t *mask;
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u_int64_t saved_mask;
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mask = &cchip->dim0.reg;
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saved_mask = *mask;
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saved_mask |= (1UL << (unsigned long)irq);
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*mask = saved_mask;
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alpha_mb();
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alpha_mb();
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saved_mask = *mask;
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alpha_mb();
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alpha_mb();
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}
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static void
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tsunami_intr_disable(int irq)
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{
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volatile u_int64_t *mask;
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u_int64_t saved_mask;
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mask = &cchip->dim0.reg;
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saved_mask = *mask;
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saved_mask &= ~(1UL << (unsigned long)irq);
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*mask = saved_mask;
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alpha_mb();
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saved_mask = *mask;
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alpha_mb();
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alpha_mb();
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}
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DRIVER_MODULE(tsunami, root, tsunami_driver, tsunami_devclass, 0, 0);
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