517904de5c
This controller supports 2.5G/1G/100MB/10MB speeds, and allows
tx/rx checksum offload, TSO, LRO, and multi-queue operation.
The driver was derived from code contributed by Intel, and modified
by Netgate to fit into the iflib framework.
Thanks to Mike Karels for testing and feedback on the driver.
Reviewed by: bcr (manpages), kbowling, scottl, erj
MFC after: 1 month
Relnotes: yes
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D30668
113 lines
4.6 KiB
C
113 lines
4.6 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* $FreeBSD$
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*/
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#ifndef _IGC_I225_H_
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#define _IGC_I225_H_
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bool igc_get_flash_presence_i225(struct igc_hw *hw);
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s32 igc_update_flash_i225(struct igc_hw *hw);
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s32 igc_update_nvm_checksum_i225(struct igc_hw *hw);
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s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw);
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s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset,
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u16 words, u16 *data);
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s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset,
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u16 words, u16 *data);
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s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw,
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u32 burst_counter);
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s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode,
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u32 address);
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s32 igc_check_for_link_i225(struct igc_hw *hw);
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s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask);
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void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask);
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s32 igc_init_hw_i225(struct igc_hw *hw);
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s32 igc_setup_copper_link_i225(struct igc_hw *hw);
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s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active);
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s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active);
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s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
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bool adv100M);
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#define ID_LED_DEFAULT_I225 ((ID_LED_OFF1_ON2 << 8) | \
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(ID_LED_DEF1_DEF2 << 4) | \
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(ID_LED_OFF1_OFF2))
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#define ID_LED_DEFAULT_I225_SERDES ((ID_LED_DEF1_DEF2 << 8) | \
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(ID_LED_DEF1_DEF2 << 4) | \
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(ID_LED_OFF1_ON2))
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/* NVM offset defaults for I225 devices */
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#define NVM_INIT_CTRL_2_DEFAULT_I225 0X7243
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#define NVM_INIT_CTRL_4_DEFAULT_I225 0x00C1
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#define NVM_LED_1_CFG_DEFAULT_I225 0x0184
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#define NVM_LED_0_2_CFG_DEFAULT_I225 0x200C
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#define IGC_MRQC_ENABLE_RSS_4Q 0x00000002
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#define IGC_MRQC_ENABLE_VMDQ 0x00000003
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#define IGC_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
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#define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
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#define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
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#define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
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#define IGC_I225_SHADOW_RAM_SIZE 4096
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#define IGC_I225_ERASE_CMD_OPCODE 0x02000000
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#define IGC_I225_WRITE_CMD_OPCODE 0x01000000
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#define IGC_FLSWCTL_DONE 0x40000000
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#define IGC_FLSWCTL_CMDV 0x10000000
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/* SRRCTL bit definitions */
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#define IGC_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
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#define IGC_SRRCTL_DESCTYPE_LEGACY 0x00000000
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#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
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#define IGC_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
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#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
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#define IGC_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
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#define IGC_SRRCTL_DESCTYPE_MASK 0x0E000000
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#define IGC_SRRCTL_DROP_EN 0x80000000
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#define IGC_SRRCTL_BSIZEPKT_MASK 0x0000007F
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#define IGC_SRRCTL_BSIZEHDR_MASK 0x00003F00
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#define IGC_RXDADV_RSSTYPE_MASK 0x0000000F
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#define IGC_RXDADV_RSSTYPE_SHIFT 12
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#define IGC_RXDADV_HDRBUFLEN_MASK 0x7FE0
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#define IGC_RXDADV_HDRBUFLEN_SHIFT 5
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#define IGC_RXDADV_SPLITHEADER_EN 0x00001000
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#define IGC_RXDADV_SPH 0x8000
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#define IGC_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
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#define IGC_RXDADV_ERR_HBO 0x00800000
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/* RSS Hash results */
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#define IGC_RXDADV_RSSTYPE_NONE 0x00000000
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#define IGC_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
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#define IGC_RXDADV_RSSTYPE_IPV4 0x00000002
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#define IGC_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
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#define IGC_RXDADV_RSSTYPE_IPV6_EX 0x00000004
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#define IGC_RXDADV_RSSTYPE_IPV6 0x00000005
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#define IGC_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
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#define IGC_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
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#define IGC_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
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#define IGC_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
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/* RSS Packet Types as indicated in the receive descriptor */
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#define IGC_RXDADV_PKTTYPE_ILMASK 0x000000F0
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#define IGC_RXDADV_PKTTYPE_TLMASK 0x00000F00
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#define IGC_RXDADV_PKTTYPE_NONE 0x00000000
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#define IGC_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPV4 hdr present */
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#define IGC_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPV4 hdr + extensions */
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#define IGC_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPV6 hdr present */
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#define IGC_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPV6 hdr + extensions */
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#define IGC_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
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#define IGC_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
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#define IGC_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
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#define IGC_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
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#define IGC_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
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#define IGC_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
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#define IGC_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
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#define IGC_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
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#define IGC_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
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#define IGC_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
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#endif
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