517904de5c
This controller supports 2.5G/1G/100MB/10MB speeds, and allows
tx/rx checksum offload, TSO, LRO, and multi-queue operation.
The driver was derived from code contributed by Intel, and modified
by Netgate to fit into the iflib framework.
Thanks to Mike Karels for testing and feedback on the driver.
Reviewed by: bcr (manpages), kbowling, scottl, erj
MFC after: 1 month
Relnotes: yes
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D30668
134 lines
4.2 KiB
C
134 lines
4.2 KiB
C
/*-
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* Copyright 2021 Intel Corp
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* Copyright 2021 Rubicon Communications, LLC (Netgate)
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* $FreeBSD$
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*/
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#ifndef _FREEBSD_OS_H_
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#define _FREEBSD_OS_H_
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/mbuf.h>
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#include <sys/protosw.h>
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#include <sys/socket.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/iflib.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/clock.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#define usec_delay(x) DELAY(x)
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#define usec_delay_irq(x) usec_delay(x)
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#define msec_delay(x) DELAY(1000*(x))
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#define msec_delay_irq(x) DELAY(1000*(x))
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/* Enable/disable debugging statements in shared code */
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#define DBG 0
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#define DEBUGOUT(...) \
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do { if (DBG) printf(__VA_ARGS__); } while (0)
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#define DEBUGOUT1(...) DEBUGOUT(__VA_ARGS__)
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#define DEBUGOUT2(...) DEBUGOUT(__VA_ARGS__)
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#define DEBUGOUT3(...) DEBUGOUT(__VA_ARGS__)
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#define DEBUGOUT7(...) DEBUGOUT(__VA_ARGS__)
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#define DEBUGFUNC(F) DEBUGOUT(F "\n")
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typedef uint64_t u64;
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef int64_t s64;
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typedef int32_t s32;
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typedef int16_t s16;
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typedef int8_t s8;
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#define __le16 u16
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#define __le32 u32
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#define __le64 u64
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struct igc_osdep
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{
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bus_space_tag_t mem_bus_space_tag;
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bus_space_handle_t mem_bus_space_handle;
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bus_space_tag_t io_bus_space_tag;
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bus_space_handle_t io_bus_space_handle;
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bus_space_tag_t flash_bus_space_tag;
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bus_space_handle_t flash_bus_space_handle;
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device_t dev;
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if_ctx_t ctx;
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};
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#define IGC_REGISTER(hw, reg) reg
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#define IGC_WRITE_FLUSH(a) IGC_READ_REG(a, IGC_STATUS)
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/* Read from an absolute offset in the adapter's memory space */
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#define IGC_READ_OFFSET(hw, offset) \
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bus_space_read_4(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct igc_osdep *)(hw)->back)->mem_bus_space_handle, offset)
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/* Write to an absolute offset in the adapter's memory space */
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#define IGC_WRITE_OFFSET(hw, offset, value) \
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bus_space_write_4(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct igc_osdep *)(hw)->back)->mem_bus_space_handle, offset, value)
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/* Register READ/WRITE macros */
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#define IGC_READ_REG(hw, reg) \
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bus_space_read_4(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct igc_osdep *)(hw)->back)->mem_bus_space_handle, \
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IGC_REGISTER(hw, reg))
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#define IGC_WRITE_REG(hw, reg, value) \
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bus_space_write_4(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct igc_osdep *)(hw)->back)->mem_bus_space_handle, \
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IGC_REGISTER(hw, reg), value)
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#define IGC_READ_REG_ARRAY(hw, reg, index) \
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bus_space_read_4(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct igc_osdep *)(hw)->back)->mem_bus_space_handle, \
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IGC_REGISTER(hw, reg) + ((index)<< 2))
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#define IGC_WRITE_REG_ARRAY(hw, reg, index, value) \
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bus_space_write_4(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct igc_osdep *)(hw)->back)->mem_bus_space_handle, \
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IGC_REGISTER(hw, reg) + ((index)<< 2), value)
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#define IGC_READ_REG_ARRAY_DWORD IGC_READ_REG_ARRAY
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#define IGC_WRITE_REG_ARRAY_DWORD IGC_WRITE_REG_ARRAY
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#define IGC_READ_REG_ARRAY_BYTE(hw, reg, index) \
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bus_space_read_1(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct igc_osdep *)(hw)->back)->mem_bus_space_handle, \
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IGC_REGISTER(hw, reg) + index)
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#define IGC_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \
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bus_space_write_1(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct igc_osdep *)(hw)->back)->mem_bus_space_handle, \
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IGC_REGISTER(hw, reg) + index, value)
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#define IGC_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \
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bus_space_write_2(((struct igc_osdep *)(hw)->back)->mem_bus_space_tag, \
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((struct igc_osdep *)(hw)->back)->mem_bus_space_handle, \
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IGC_REGISTER(hw, reg) + (index << 1), value)
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#endif /* _FREEBSD_OS_H_ */
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