736 lines
18 KiB
C
736 lines
18 KiB
C
/*-
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* Copyright (C) 2008-2010 Nathan Whitehorn
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/pciio.h>
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#include <sys/rman.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/bus.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/openpicreg.h>
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#include <machine/openpicvar.h>
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#include <machine/pio.h>
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#include <machine/resource.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <powerpc/ofw/ofw_pci.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include "pcib_if.h"
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#include "pic_if.h"
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/*
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* IBM CPC9X5 Hypertransport Device interface.
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*/
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static int cpcht_probe(device_t);
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static int cpcht_attach(device_t);
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static void cpcht_configure_htbridge(device_t, phandle_t);
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/*
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* pcib interface.
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*/
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static u_int32_t cpcht_read_config(device_t, u_int, u_int, u_int,
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u_int, int);
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static void cpcht_write_config(device_t, u_int, u_int, u_int,
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u_int, u_int32_t, int);
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static int cpcht_route_interrupt(device_t, device_t, int);
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static int cpcht_alloc_msi(device_t dev, device_t child,
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int count, int maxcount, int *irqs);
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static int cpcht_release_msi(device_t dev, device_t child,
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int count, int *irqs);
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static int cpcht_alloc_msix(device_t dev, device_t child,
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int *irq);
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static int cpcht_release_msix(device_t dev, device_t child,
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int irq);
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static int cpcht_map_msi(device_t dev, device_t child,
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int irq, uint64_t *addr, uint32_t *data);
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/*
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* Driver methods.
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*/
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static device_method_t cpcht_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, cpcht_probe),
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DEVMETHOD(device_attach, cpcht_attach),
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/* pcib interface */
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DEVMETHOD(pcib_read_config, cpcht_read_config),
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DEVMETHOD(pcib_write_config, cpcht_write_config),
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DEVMETHOD(pcib_route_interrupt, cpcht_route_interrupt),
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DEVMETHOD(pcib_alloc_msi, cpcht_alloc_msi),
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DEVMETHOD(pcib_release_msi, cpcht_release_msi),
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DEVMETHOD(pcib_alloc_msix, cpcht_alloc_msix),
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DEVMETHOD(pcib_release_msix, cpcht_release_msix),
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DEVMETHOD(pcib_map_msi, cpcht_map_msi),
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DEVMETHOD_END
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};
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struct cpcht_irq {
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enum {
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IRQ_NONE, IRQ_HT, IRQ_MSI, IRQ_INTERNAL
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} irq_type;
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int ht_source;
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vm_offset_t ht_base;
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vm_offset_t apple_eoi;
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uint32_t eoi_data;
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int edge;
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};
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static struct cpcht_irq *cpcht_irqmap = NULL;
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uint32_t cpcht_msipic = 0;
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struct cpcht_softc {
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struct ofw_pci_softc pci_sc;
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vm_offset_t sc_data;
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uint64_t sc_populated_slots;
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struct cpcht_irq htirq_map[128];
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struct mtx htirq_mtx;
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};
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static devclass_t cpcht_devclass;
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DEFINE_CLASS_1(pcib, cpcht_driver, cpcht_methods, sizeof(struct cpcht_softc),
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ofw_pci_driver);
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DRIVER_MODULE(cpcht, nexus, cpcht_driver, cpcht_devclass, 0, 0);
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#define CPCHT_IOPORT_BASE 0xf4000000UL /* Hardwired */
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#define CPCHT_IOPORT_SIZE 0x00400000UL
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#define HTAPIC_REQUEST_EOI 0x20
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#define HTAPIC_TRIGGER_LEVEL 0x02
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#define HTAPIC_MASK 0x01
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static int
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cpcht_probe(device_t dev)
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{
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const char *type, *compatible;
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type = ofw_bus_get_type(dev);
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compatible = ofw_bus_get_compat(dev);
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if (type == NULL || compatible == NULL)
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return (ENXIO);
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if (strcmp(type, "ht") != 0)
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return (ENXIO);
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if (strcmp(compatible, "u3-ht") != 0)
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return (ENXIO);
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device_set_desc(dev, "IBM CPC9X5 HyperTransport Tunnel");
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return (0);
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}
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static int
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cpcht_attach(device_t dev)
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{
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struct cpcht_softc *sc;
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phandle_t node, child;
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u_int32_t reg[3];
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int i;
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node = ofw_bus_get_node(dev);
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sc = device_get_softc(dev);
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if (OF_getprop(node, "reg", reg, sizeof(reg)) < 12)
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return (ENXIO);
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if (OF_getproplen(node, "ranges") <= 0)
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sc->pci_sc.sc_quirks = OFW_PCI_QUIRK_RANGES_ON_CHILDREN;
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sc->sc_populated_slots = 0;
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sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1], reg[2]);
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/*
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* Set up the resource manager and the HT->MPIC mapping. For cpcht,
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* the ranges are properties of the child bridges, and this is also
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* where we get the HT interrupts properties.
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*/
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#if 0
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/* I/O port mappings are usually not in the device tree */
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rman_manage_region(&sc->pci_sc.sc_io_rman, 0, CPCHT_IOPORT_SIZE - 1);
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#endif
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bzero(sc->htirq_map, sizeof(sc->htirq_map));
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mtx_init(&sc->htirq_mtx, "cpcht irq", NULL, MTX_DEF);
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for (i = 0; i < 8; i++)
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sc->htirq_map[i].irq_type = IRQ_INTERNAL;
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for (child = OF_child(node); child != 0; child = OF_peer(child))
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cpcht_configure_htbridge(dev, child);
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/* Now make the mapping table available to the MPIC */
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cpcht_irqmap = sc->htirq_map;
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return (ofw_pci_attach(dev));
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}
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static void
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cpcht_configure_htbridge(device_t dev, phandle_t child)
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{
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struct cpcht_softc *sc;
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struct ofw_pci_register pcir;
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int ptr, nextptr;
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uint32_t vend, val;
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int i, nirq, irq;
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u_int b, f, s;
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sc = device_get_softc(dev);
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if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
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return;
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b = OFW_PCI_PHYS_HI_BUS(pcir.phys_hi);
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s = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
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f = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
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/*
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* Mark this slot is populated. The remote south bridge does
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* not like us talking to unpopulated slots on the root bus.
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*/
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sc->sc_populated_slots |= (1 << s);
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/*
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* Next build up any HT->MPIC mappings for this sub-bus. One would
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* naively hope that enabling, disabling, and EOIing interrupts would
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* cause the appropriate HT bus transactions to that effect. This is
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* not the case.
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*
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* Instead, we have to muck about on the HT peer's root PCI bridges,
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* figure out what interrupts they send, enable them, and cache
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* the location of their WaitForEOI registers so that we can
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* send EOIs later.
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*/
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/* All the devices we are interested in have caps */
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if (!(PCIB_READ_CONFIG(dev, b, s, f, PCIR_STATUS, 2)
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& PCIM_STATUS_CAPPRESENT))
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return;
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nextptr = PCIB_READ_CONFIG(dev, b, s, f, PCIR_CAP_PTR, 1);
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while (nextptr != 0) {
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ptr = nextptr;
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nextptr = PCIB_READ_CONFIG(dev, b, s, f,
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ptr + PCICAP_NEXTPTR, 1);
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/* Find the HT IRQ capabilities */
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if (PCIB_READ_CONFIG(dev, b, s, f,
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ptr + PCICAP_ID, 1) != PCIY_HT)
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continue;
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val = PCIB_READ_CONFIG(dev, b, s, f, ptr + PCIR_HT_COMMAND, 2);
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if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_INTERRUPT)
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continue;
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/* Ask for the IRQ count */
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PCIB_WRITE_CONFIG(dev, b, s, f, ptr + PCIR_HT_COMMAND, 0x1, 1);
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nirq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4);
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nirq = ((nirq >> 16) & 0xff) + 1;
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device_printf(dev, "%d HT IRQs on device %d.%d\n", nirq, s, f);
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for (i = 0; i < nirq; i++) {
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PCIB_WRITE_CONFIG(dev, b, s, f,
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ptr + PCIR_HT_COMMAND, 0x10 + (i << 1), 1);
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irq = PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4);
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/*
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* Mask this interrupt for now.
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*/
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PCIB_WRITE_CONFIG(dev, b, s, f, ptr + 4,
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irq | HTAPIC_MASK, 4);
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irq = (irq >> 16) & 0xff;
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sc->htirq_map[irq].irq_type = IRQ_HT;
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sc->htirq_map[irq].ht_source = i;
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sc->htirq_map[irq].ht_base = sc->sc_data +
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(((((s & 0x1f) << 3) | (f & 0x07)) << 8) | (ptr));
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PCIB_WRITE_CONFIG(dev, b, s, f,
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ptr + PCIR_HT_COMMAND, 0x11 + (i << 1), 1);
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sc->htirq_map[irq].eoi_data =
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PCIB_READ_CONFIG(dev, b, s, f, ptr + 4, 4) |
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0x80000000;
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/*
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* Apple uses a non-compliant IO/APIC that differs
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* in how we signal EOIs. Check if this device was
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* made by Apple, and act accordingly.
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*/
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vend = PCIB_READ_CONFIG(dev, b, s, f,
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PCIR_DEVVENDOR, 4);
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if ((vend & 0xffff) == 0x106b)
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sc->htirq_map[irq].apple_eoi =
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(sc->htirq_map[irq].ht_base - ptr) + 0x60;
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}
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}
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}
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static u_int32_t
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cpcht_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
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int width)
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{
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struct cpcht_softc *sc;
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vm_offset_t caoff;
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sc = device_get_softc(dev);
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caoff = sc->sc_data +
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(((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg);
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if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0))
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return (0xffffffff);
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if (bus > 0)
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caoff += 0x01000000UL + (bus << 16);
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switch (width) {
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case 1:
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return (in8rb(caoff));
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break;
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case 2:
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return (in16rb(caoff));
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break;
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case 4:
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return (in32rb(caoff));
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break;
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}
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return (0xffffffff);
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}
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static void
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cpcht_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, u_int32_t val, int width)
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{
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struct cpcht_softc *sc;
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vm_offset_t caoff;
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sc = device_get_softc(dev);
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caoff = sc->sc_data +
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(((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg);
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if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0))
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return;
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if (bus > 0)
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caoff += 0x01000000UL + (bus << 16);
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switch (width) {
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case 1:
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out8rb(caoff, val);
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break;
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case 2:
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out16rb(caoff, val);
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break;
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case 4:
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out32rb(caoff, val);
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break;
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}
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}
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static int
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cpcht_route_interrupt(device_t bus, device_t dev, int pin)
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{
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return (pin);
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}
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static int
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cpcht_alloc_msi(device_t dev, device_t child, int count, int maxcount,
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int *irqs)
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{
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struct cpcht_softc *sc;
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int i, j;
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sc = device_get_softc(dev);
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j = 0;
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/* Bail if no MSI PIC yet */
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if (cpcht_msipic == 0)
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return (ENXIO);
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mtx_lock(&sc->htirq_mtx);
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for (i = 8; i < 124 - count; i++) {
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for (j = 0; j < count; j++) {
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if (sc->htirq_map[i+j].irq_type != IRQ_NONE)
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break;
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}
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if (j == count)
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break;
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i += j; /* We know there isn't a large enough run */
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}
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if (j != count) {
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mtx_unlock(&sc->htirq_mtx);
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return (ENXIO);
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}
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for (j = 0; j < count; j++) {
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irqs[j] = MAP_IRQ(cpcht_msipic, i+j);
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sc->htirq_map[i+j].irq_type = IRQ_MSI;
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}
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mtx_unlock(&sc->htirq_mtx);
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return (0);
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}
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static int
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cpcht_release_msi(device_t dev, device_t child, int count, int *irqs)
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{
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struct cpcht_softc *sc;
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int i;
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sc = device_get_softc(dev);
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mtx_lock(&sc->htirq_mtx);
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for (i = 0; i < count; i++)
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sc->htirq_map[irqs[i] & 0xff].irq_type = IRQ_NONE;
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mtx_unlock(&sc->htirq_mtx);
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return (0);
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}
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static int
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cpcht_alloc_msix(device_t dev, device_t child, int *irq)
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{
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struct cpcht_softc *sc;
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int i;
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sc = device_get_softc(dev);
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/* Bail if no MSI PIC yet */
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if (cpcht_msipic == 0)
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return (ENXIO);
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mtx_lock(&sc->htirq_mtx);
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for (i = 8; i < 124; i++) {
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if (sc->htirq_map[i].irq_type == IRQ_NONE) {
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sc->htirq_map[i].irq_type = IRQ_MSI;
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*irq = MAP_IRQ(cpcht_msipic, i);
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mtx_unlock(&sc->htirq_mtx);
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return (0);
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}
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}
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mtx_unlock(&sc->htirq_mtx);
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return (ENXIO);
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}
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static int
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cpcht_release_msix(device_t dev, device_t child, int irq)
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{
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struct cpcht_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->htirq_mtx);
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sc->htirq_map[irq & 0xff].irq_type = IRQ_NONE;
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mtx_unlock(&sc->htirq_mtx);
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return (0);
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}
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static int
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cpcht_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
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uint32_t *data)
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{
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device_t pcib;
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struct pci_devinfo *dinfo;
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struct pcicfg_ht *ht = NULL;
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for (pcib = child; pcib != dev; pcib =
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device_get_parent(device_get_parent(pcib))) {
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dinfo = device_get_ivars(pcib);
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ht = &dinfo->cfg.ht;
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if (ht == NULL)
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continue;
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}
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if (ht == NULL)
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return (ENXIO);
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*addr = ht->ht_msiaddr;
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*data = irq & 0xff;
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return (0);
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}
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/*
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* Driver for the integrated MPIC on U3/U4 (CPC925/CPC945)
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*/
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static int openpic_cpcht_probe(device_t);
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static int openpic_cpcht_attach(device_t);
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static void openpic_cpcht_config(device_t, u_int irq,
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enum intr_trigger trig, enum intr_polarity pol);
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static void openpic_cpcht_enable(device_t, u_int irq, u_int vector);
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static void openpic_cpcht_unmask(device_t, u_int irq);
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static void openpic_cpcht_eoi(device_t, u_int irq);
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static device_method_t openpic_cpcht_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, openpic_cpcht_probe),
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DEVMETHOD(device_attach, openpic_cpcht_attach),
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/* PIC interface */
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DEVMETHOD(pic_bind, openpic_bind),
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DEVMETHOD(pic_config, openpic_cpcht_config),
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DEVMETHOD(pic_dispatch, openpic_dispatch),
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DEVMETHOD(pic_enable, openpic_cpcht_enable),
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DEVMETHOD(pic_eoi, openpic_cpcht_eoi),
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DEVMETHOD(pic_ipi, openpic_ipi),
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DEVMETHOD(pic_mask, openpic_mask),
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DEVMETHOD(pic_unmask, openpic_cpcht_unmask),
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{ 0, 0 },
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};
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struct openpic_cpcht_softc {
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struct openpic_softc sc_openpic;
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struct mtx sc_ht_mtx;
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};
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static driver_t openpic_cpcht_driver = {
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"htpic",
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openpic_cpcht_methods,
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sizeof(struct openpic_cpcht_softc),
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};
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DRIVER_MODULE(openpic, unin, openpic_cpcht_driver, openpic_devclass, 0, 0);
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static int
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openpic_cpcht_probe(device_t dev)
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{
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const char *type = ofw_bus_get_type(dev);
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if (strcmp(type, "open-pic") != 0)
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return (ENXIO);
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device_set_desc(dev, OPENPIC_DEVSTR);
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return (0);
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}
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static int
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openpic_cpcht_attach(device_t dev)
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{
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struct openpic_cpcht_softc *sc;
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phandle_t node;
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int err, irq;
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node = ofw_bus_get_node(dev);
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err = openpic_common_attach(dev, node);
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if (err != 0)
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return (err);
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/*
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* The HT APIC stuff is not thread-safe, so we need a mutex to
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* protect it.
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*/
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sc = device_get_softc(dev);
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mtx_init(&sc->sc_ht_mtx, "htpic", NULL, MTX_SPIN);
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/*
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* Interrupts 0-3 are internally sourced and are level triggered
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* active low. Interrupts 4-123 are connected to a pulse generator
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* and should be programmed as edge triggered low-to-high.
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*
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* IBM CPC945 Manual, Section 9.3.
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*/
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for (irq = 0; irq < 4; irq++)
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openpic_config(dev, irq, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
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for (irq = 4; irq < 124; irq++)
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openpic_config(dev, irq, INTR_TRIGGER_EDGE, INTR_POLARITY_LOW);
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/*
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* Use this PIC for MSI only if it is the root PIC. This may not
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* be necessary, but Linux does it, and I cannot find any U3 machines
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* with MSI devices to test.
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*/
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if (dev == root_pic)
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cpcht_msipic = node;
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return (0);
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}
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static void
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openpic_cpcht_config(device_t dev, u_int irq, enum intr_trigger trig,
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enum intr_polarity pol)
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{
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struct openpic_cpcht_softc *sc;
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uint32_t ht_irq;
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/*
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* The interrupt settings for the MPIC are completely determined
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* by the internal wiring in the northbridge. Real changes to these
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* settings need to be negotiated with the remote IO-APIC on the HT
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* link.
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*/
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sc = device_get_softc(dev);
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if (cpcht_irqmap != NULL && irq < 128 &&
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cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) {
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mtx_lock_spin(&sc->sc_ht_mtx);
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/* Program the data port */
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out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
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0x10 + (cpcht_irqmap[irq].ht_source << 1));
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/* Grab the IRQ config register */
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ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4);
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/* Mask the IRQ while we fiddle settings */
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out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq | HTAPIC_MASK);
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/* Program the interrupt sense */
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ht_irq &= ~(HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI);
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if (trig == INTR_TRIGGER_EDGE) {
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cpcht_irqmap[irq].edge = 1;
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} else {
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cpcht_irqmap[irq].edge = 0;
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ht_irq |= HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI;
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}
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out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq);
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mtx_unlock_spin(&sc->sc_ht_mtx);
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}
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}
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static void
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openpic_cpcht_enable(device_t dev, u_int irq, u_int vec)
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{
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struct openpic_cpcht_softc *sc;
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uint32_t ht_irq;
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openpic_enable(dev, irq, vec);
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sc = device_get_softc(dev);
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if (cpcht_irqmap != NULL && irq < 128 &&
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cpcht_irqmap[irq].ht_base > 0) {
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mtx_lock_spin(&sc->sc_ht_mtx);
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/* Program the data port */
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out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
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0x10 + (cpcht_irqmap[irq].ht_source << 1));
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/* Unmask the interrupt */
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ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4);
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ht_irq &= ~HTAPIC_MASK;
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out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq);
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mtx_unlock_spin(&sc->sc_ht_mtx);
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}
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openpic_cpcht_eoi(dev, irq);
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}
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static void
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openpic_cpcht_unmask(device_t dev, u_int irq)
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{
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struct openpic_cpcht_softc *sc;
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uint32_t ht_irq;
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openpic_unmask(dev, irq);
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sc = device_get_softc(dev);
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if (cpcht_irqmap != NULL && irq < 128 &&
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cpcht_irqmap[irq].ht_base > 0) {
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mtx_lock_spin(&sc->sc_ht_mtx);
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/* Program the data port */
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out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
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0x10 + (cpcht_irqmap[irq].ht_source << 1));
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/* Unmask the interrupt */
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ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4);
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ht_irq &= ~HTAPIC_MASK;
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out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq);
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mtx_unlock_spin(&sc->sc_ht_mtx);
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}
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openpic_cpcht_eoi(dev, irq);
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}
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static void
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openpic_cpcht_eoi(device_t dev, u_int irq)
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{
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struct openpic_cpcht_softc *sc;
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uint32_t off, mask;
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if (irq == 255)
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return;
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sc = device_get_softc(dev);
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if (cpcht_irqmap != NULL && irq < 128 &&
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cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) {
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/* If this is an HT IRQ, acknowledge it at the remote APIC */
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if (cpcht_irqmap[irq].apple_eoi) {
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off = (cpcht_irqmap[irq].ht_source >> 3) & ~3;
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mask = 1 << (cpcht_irqmap[irq].ht_source & 0x1f);
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out32rb(cpcht_irqmap[irq].apple_eoi + off, mask);
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} else {
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mtx_lock_spin(&sc->sc_ht_mtx);
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out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
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0x11 + (cpcht_irqmap[irq].ht_source << 1));
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out32rb(cpcht_irqmap[irq].ht_base + 4,
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cpcht_irqmap[irq].eoi_data);
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mtx_unlock_spin(&sc->sc_ht_mtx);
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}
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}
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openpic_eoi(dev, irq);
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}
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