caeff9a3c2
On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the common bhnd(4) core drivers; we now register an INTRNG child PIC that handles routing of backplane interrupt vectors via the MIPS core. On BHND PCI devices, backplane interrupt vectors are now routed to the PCI/PCIe host bridge core when bus_setup_intr() is called, where they are dispatched by the PCI core via a host interrupt (e.g. INTx/MSI). The bhndb(4) bridge driver tracks registered interrupt handlers for the bridged bhnd(4) devices and manages backplane interrupt routing, while delegating actual bus interrupt setup/teardown to the parent bus on behalf of the bridged cores. Approved by: adrian (mentor, implicit) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D12518
115 lines
4.1 KiB
C
115 lines
4.1 KiB
C
/*-
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* Copyright (c) 2017 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Landon Fuller under sponsorship from
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* the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _MIPS_BROADCOM_BCM_MIPSVAR_H_
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#define _MIPS_BROADCOM_BCM_MIPSVAR_H_
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <sys/lock.h>
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#include <machine/intr.h>
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DECLARE_CLASS(bcm_mips_driver);
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struct bcm_mips_irqsrc;
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struct bcm_mips_softc;
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#define BCM_MIPS_NINTR 32 /**< maximum number of addressable backplane interrupt vectors */
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#define BCM_MIPS_IRQ_SHARED 0 /**< MIPS CPU IRQ reserved for shared interrupt handling */
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#define INTR_MAP_DATA_BCM_MIPS INTR_MAP_DATA_PLAT_2 /**< Broadcom MIPS PIC interrupt map data type */
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int bcm_mips_attach(device_t dev, u_int num_cpuirqs, u_int timer_irq,
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driver_filter_t filter);
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int bcm_mips_detach(device_t dev);
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/**
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* Broadcom MIPS PIC interrupt map data.
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*/
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struct bcm_mips_intr_map_data {
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struct intr_map_data mdata;
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u_int ivec; /**< bus interrupt vector */
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};
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/**
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* Nested MIPS CPU interrupt handler state.
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*/
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struct bcm_mips_cpuirq {
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struct bcm_mips_softc *sc; /**< driver instance state, or NULL if uninitialized. */
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u_int mips_irq; /**< mips hardware interrupt number (relative to NSOFT_IRQ) */
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int irq_rid; /**< mips IRQ resource id, or -1 if this entry is unavailable */
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struct resource *irq_res; /**< mips interrupt resource */
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void *irq_cookie; /**< mips interrupt handler cookie, or NULL */
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struct bcm_mips_irqsrc *isrc_solo; /**< solo isrc assigned to this interrupt, or NULL */
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u_int refs; /**< isrc consumer refcount */
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};
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/**
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* Broadcom MIPS PIC interrupt source definition.
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*/
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struct bcm_mips_irqsrc {
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struct intr_irqsrc isrc;
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u_int ivec; /**< bus interrupt vector */
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u_int refs; /**< active reference count */
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struct bcm_mips_cpuirq *cpuirq; /**< assigned MIPS HW IRQ, or NULL if no assignment */
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};
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/**
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* bcm_mips driver instance state. Must be first member of all subclass
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* softc structures.
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*/
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struct bcm_mips_softc {
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device_t dev;
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struct bcm_mips_cpuirq cpuirqs[NREAL_IRQS]; /**< nested CPU IRQ handlers */
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u_int num_cpuirqs; /**< number of nested CPU IRQ handlers */
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u_int timer_irq; /**< CPU timer IRQ */
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struct bcm_mips_irqsrc isrcs[BCM_MIPS_NINTR];
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struct mtx mtx;
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};
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#define BCM_MIPS_IVEC_MASK(_isrc) (1 << ((_isrc)->ivec))
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#define BCM_MIPS_LOCK_INIT(sc) \
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mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
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"bhnd mips driver lock", MTX_DEF)
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#define BCM_MIPS_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define BCM_MIPS_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define BCM_MIPS_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what)
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#define BCM_MIPS_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx)
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#endif /* _MIPS_BROADCOM_BCM_MIPSVAR_H_ */
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