ccc1e6eb49
Spliting armv5 and armv7 machdep is necessary for adding Armada38X and ArmadaXP to GENERIC config. PLATFORM framework checks SOC type in FDT and will select proper initialization function implementation during runtime. Pointers to SoC specific implementation are stored in array of platform_method_t and provided to framework by FDT_PLATFORM_DEF macro. PLATFORM framework supports also reset function. To simplify implementation cpu_reset is moved from mv_common to armv5 and armv7 machdep. Armada38X and ArmadaXP share now common list of files, so resolve all dependencies as well. Submitted by: Rafal Kozik <rk@semihalf.com> Marcin Wojtas <mw@semihalf.com> Reviewed by: mw Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14744
149 lines
4.1 KiB
C
149 lines
4.1 KiB
C
/*-
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* Copyright (c) 2015 Semihalf.
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* Copyright (c) 2015 Stormshield.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/smp.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#include <machine/platformvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/mv/mvreg.h>
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#include "pmsu.h"
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static int cpu_reset_deassert(void);
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void mv_a38x_platform_mp_setmaxid(platform_t plate);
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void mv_a38x_platform_mp_start_ap(platform_t plate);
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static int
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cpu_reset_deassert(void)
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{
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bus_space_handle_t vaddr;
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uint32_t reg;
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int rv;
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rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_CPU_RESET_BASE,
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MV_CPU_RESET_REGS_LEN, 0, &vaddr);
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if (rv != 0)
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return (rv);
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/* CPU1 is held at reset by default - clear assert bit to release it */
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reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1));
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reg &= ~CPU_RESET_ASSERT;
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bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg);
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bus_space_unmap(fdtbus_bs_tag, vaddr, MV_CPU_RESET_REGS_LEN);
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return (0);
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}
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static int
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platform_cnt_cpus(void)
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{
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bus_space_handle_t vaddr_scu;
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phandle_t cpus_node, child;
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char device_type[16];
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int fdt_cpu_count = 0;
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int reg_cpu_count = 0;
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uint32_t val;
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int rv;
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cpus_node = OF_finddevice("/cpus");
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if (cpus_node == -1) {
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/* Default is one core */
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mp_ncpus = 1;
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return (0);
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}
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/* Get number of 'cpu' nodes from FDT */
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for (child = OF_child(cpus_node); child != 0; child = OF_peer(child)) {
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/* Check if child is a CPU */
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memset(device_type, 0, sizeof(device_type));
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rv = OF_getprop(child, "device_type", device_type,
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sizeof(device_type) - 1);
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if (rv < 0)
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continue;
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if (strcmp(device_type, "cpu") != 0)
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continue;
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fdt_cpu_count++;
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}
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/* Get number of CPU cores from SCU register to cross-check with FDT */
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rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
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MV_SCU_REGS_LEN, 0, &vaddr_scu);
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if (rv != 0) {
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/* Default is one core */
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mp_ncpus = 1;
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return (0);
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}
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val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CONFIG);
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bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
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reg_cpu_count = (val & SCU_CFG_REG_NCPU_MASK) + 1;
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/* Set mp_ncpus to number of cpus in FDT unless SOC contains only one */
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mp_ncpus = min(reg_cpu_count, fdt_cpu_count);
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/* mp_ncpus must be at least 1 */
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mp_ncpus = max(1, mp_ncpus);
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return (mp_ncpus);
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}
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void
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mv_a38x_platform_mp_setmaxid(platform_t plate)
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{
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/* Armada38x family supports maximum 2 cores */
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mp_ncpus = platform_cnt_cpus();
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mp_maxid = mp_ncpus - 1;
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}
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void
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mv_a38x_platform_mp_start_ap(platform_t plate)
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{
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int rv;
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/* Write secondary entry address to PMSU register */
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rv = pmsu_boot_secondary_cpu();
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if (rv != 0)
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return;
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/* Release CPU1 from reset */
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cpu_reset_deassert();
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}
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