This is needed with the pl011 driver. Before this change it would default to a shift of 0, however the hardware places the registers at 4-byte addresses meaning the value should be 2. This patch fixes this for the pl011 when configured using the fdt. The other drivers have a default value of 0 to keep this a no-op. MFC after: 1 week |
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.. | ||
files.rt305x | ||
obio.c | ||
obiovar.h | ||
rt305x_dotg.c | ||
rt305x_gpio.c | ||
rt305x_gpio.h | ||
rt305x_gpiovar.h | ||
rt305x_ic.c | ||
rt305x_icvar.h | ||
rt305x_machdep.c | ||
rt305x_sysctl.c | ||
rt305x_sysctlvar.h | ||
rt305xreg.h | ||
rt_swreg.h | ||
std.rt305x | ||
uart_bus_rt305x.c | ||
uart_cpu_rt305x.c | ||
uart_dev_rt305x.c | ||
uart_dev_rt305x.h |