548d35fd69
Features: Jumbo frames (up to 9600), LRO (Large Receive Offload),
TSO (TCP segmentation offload), RTH (Receive Traffic Hash).
Submitted by: Sriram Rapuru at Exar
MFC after: 2 weeks
689 lines
23 KiB
C
689 lines
23 KiB
C
/*-
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* Copyright(c) 2002-2011 Exar Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification are permitted provided the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Exar Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#ifndef VXGE_HAL_MGMT_H
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#define VXGE_HAL_MGMT_H
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__EXTERN_BEGIN_DECLS
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/*
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* struct vxge_hal_mgmt_about_info_t - About info.
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* @vendor: PCI Vendor ID.
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* @device: PCI Device ID.
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* @subsys_vendor: PCI Subsystem Vendor ID.
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* @subsys_device: PCI Subsystem Device ID.
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* @board_rev: PCI Board revision, e.g. 3 - for Xena 3.
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* @vendor_name: Exar Corp.
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* @chip_name: X3100.
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* @media: Fiber, copper.
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* @hal_major: HAL major version number.
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* @hal_minor: HAL minor version number.
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* @hal_fix: HAL fix number.
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* @hal_build: HAL build number.
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* @ll_major: Link-layer ULD major version number.
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* @ll_minor: Link-layer ULD minor version number.
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* @ll_fix: Link-layer ULD fix version number.
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* @ll_build: Link-layer ULD build number.
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*/
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typedef struct vxge_hal_mgmt_about_info_t {
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u16 vendor;
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u16 device;
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u16 subsys_vendor;
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u16 subsys_device;
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u8 board_rev;
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char vendor_name[16];
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char chip_name[16];
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char media[16];
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char hal_major[4];
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char hal_minor[4];
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char hal_fix[4];
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char hal_build[16];
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char ll_major[4];
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char ll_minor[4];
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char ll_fix[4];
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char ll_build[16];
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} vxge_hal_mgmt_about_info_t;
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/*
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* vxge_hal_mgmt_about - Retrieve about info.
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* @devh: HAL device handle.
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* @about_info: Filled in by HAL. See vxge_hal_mgmt_about_info_t {}.
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* @size: Pointer to buffer containing the Size of the @buffer_info.
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* HAL will return an error if the size is smaller than
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* sizeof(vxge_hal_mgmt_about_info_t) and returns required size in this field
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*
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* Retrieve information such as PCI device and vendor IDs, board
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* revision number, HAL version number, etc.
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*
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* Returns: VXGE_HAL_OK - success;
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* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
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* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
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* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
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* VXGE_HAL_FAIL - Failed to retrieve the information.
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*
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* See also: vxge_hal_mgmt_about_info_t {}.
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*/
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vxge_hal_status_e
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vxge_hal_mgmt_about(vxge_hal_device_h devh,
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vxge_hal_mgmt_about_info_t *about_info,
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u32 *size);
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/*
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* vxge_hal_mgmt_pci_config - Retrieve PCI configuration.
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* @devh: HAL device handle.
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* @buffer: Buffer for PCI configuration space.
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* @size: Pointer to buffer containing the Size of the @buffer.
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* HAL will return an error if the size is smaller than
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* sizeof(vxge_hal_pci_config_t) and returns required size in this field
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*
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* Get PCI configuration. Permits to retrieve at run-time configuration
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* values that were used to configure the device at load-time.
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*
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* Returns: VXGE_HAL_OK - success.
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* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
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* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
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* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
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*
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*/
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vxge_hal_status_e
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vxge_hal_mgmt_pci_config(vxge_hal_device_h devh, u8 *buffer, u32 *size);
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/*
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* struct vxge_hal_mgmt_pm_cap_t - Power Management Capabilities
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* @pm_cap_ver: Version
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* @pm_cap_pme_clock: PME clock required
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* @pm_cap_aux_power: Auxilliary power support
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* @pm_cap_dsi: Device specific initialization
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* @pm_cap_aux_current: auxiliary current requirements
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* @pm_cap_cap_d0: D1 power state support
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* @pm_cap_cap_d1: D2 power state support
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* @pm_cap_pme_d0: PME# can be asserted from D3hot
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* @pm_cap_pme_d1: PME# can be asserted from D3hot
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* @pm_cap_pme_d2: PME# can be asserted from D3hot
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* @pm_cap_pme_d3_hot: PME# can be asserted from D3hot
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* @pm_cap_pme_d3_cold: PME# can be asserted from D3cold
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* @pm_ctrl_state: Current power state (D0 to D3)
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* @pm_ctrl_no_soft_reset: Devices transitioning from D3hot to D0
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* @pm_ctrl_pme_enable: PME pin enable
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* @pm_ctrl_pme_data_sel: Data select
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* @pm_ctrl_pme_data_scale: Data scale
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* @pm_ctrl_pme_status: PME pin status
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* @pm_ppb_ext_b2_b3: Stop clock when in D3hot
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* @pm_ppb_ext_ecc_en: Bus power/clock control enable
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* @pm_data_reg: state dependent data requested by pm_ctrl_pme_data_sel
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*
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* Power Management Capabilities structure
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*/
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typedef struct vxge_hal_mgmt_pm_cap_t {
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u32 pm_cap_ver;
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u32 pm_cap_pme_clock;
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u32 pm_cap_aux_power;
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u32 pm_cap_dsi;
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u32 pm_cap_aux_current;
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u32 pm_cap_cap_d0;
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u32 pm_cap_cap_d1;
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u32 pm_cap_pme_d0;
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u32 pm_cap_pme_d1;
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u32 pm_cap_pme_d2;
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u32 pm_cap_pme_d3_hot;
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u32 pm_cap_pme_d3_cold;
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u32 pm_ctrl_state;
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u32 pm_ctrl_no_soft_reset;
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u32 pm_ctrl_pme_enable;
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u32 pm_ctrl_pme_data_sel;
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u32 pm_ctrl_pme_data_scale;
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u32 pm_ctrl_pme_status;
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u32 pm_ppb_ext_b2_b3;
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u32 pm_ppb_ext_ecc_en;
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u32 pm_data_reg;
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} vxge_hal_mgmt_pm_cap_t;
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/*
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* vxge_hal_mgmt_pm_capabilities_get - Returns the pm capabilities
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* @devh: HAL device handle.
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* @pm_cap: Power Management Capabilities
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*
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* Return the pm capabilities
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*/
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vxge_hal_status_e
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vxge_hal_mgmt_pm_capabilities_get(vxge_hal_device_h devh,
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vxge_hal_mgmt_pm_cap_t *pm_cap);
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/*
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* struct vxge_hal_mgmt_sid_cap_t - Slot ID Capabilities
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* @sid_number_of_slots: Number of solts
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* @sid_first_in_chasis: First in chasis flag
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* @sid_chasis_number: Chasis Number
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*
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* Slot ID Capabilities structure
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*/
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typedef struct vxge_hal_mgmt_sid_cap_t {
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u32 sid_number_of_slots;
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u32 sid_first_in_chasis;
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u32 sid_chasis_number;
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} vxge_hal_mgmt_sid_cap_t;
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/*
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* vxge_hal_mgmt_sid_capabilities_get - Returns the sid capabilities
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* @devh: HAL device handle.
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* @sid_cap: Slot Id Capabilities
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*
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* Return the pm capabilities
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*/
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vxge_hal_status_e
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vxge_hal_mgmt_sid_capabilities_get(vxge_hal_device_h devh,
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vxge_hal_mgmt_sid_cap_t *sid_cap);
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/*
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* struct vxge_hal_mgmt_msi_cap_t - MSI Capabilities
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* @enable: 1 - MSI enabled, 0 - MSI not enabled
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* @is_pvm_capable: 1 - PVM capable, 0 - Not PVM Capable (valid for get only)
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* @is_64bit_addr_capable: 1 - 64 bit address capable, 0 - 32 bit address only
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* (valid for get only)
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* @vectors_allocated: Number of vectors allocated
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* 000-1 vectors
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* 001-2 vectors
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* 010-4 vectors
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* 011-8 vectors
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* 100-16 vectors
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* 101-32 vectors
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* @max_vectors_capable: Maximum number of vectors that can be allocated
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* (valid for get only)
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* 000-1 vectors
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* 001-2 vectors
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* 010-4 vectors
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* 011-8 vectors
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* 100-16 vectors
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* 101-32 vectors
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* @address: MSI address
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* @data: MSI Data
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* @mask_bits: For each Mask bit that is set, the function is prohibited from
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* sending the associated message
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* @pending_bits: For each Pending bit that is set, the function has a
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* pending associated message.
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*
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* MSI Capabilities structure
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*/
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typedef struct vxge_hal_mgmt_msi_cap_t {
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u32 enable;
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u32 is_pvm_capable;
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u32 is_64bit_addr_capable;
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u32 vectors_allocated;
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u32 max_vectors_capable;
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#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_1 0
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#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_2 1
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#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_4 2
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#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_8 3
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#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_16 4
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#define VXGE_HAL_MGMT_MSI_CAP_VECTORS_32 5
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u64 address;
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u16 data;
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u32 mask_bits;
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u32 pending_bits;
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} vxge_hal_mgmt_msi_cap_t;
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/*
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* vxge_hal_mgmt_msi_capabilities_get - Returns the msi capabilities
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* @devh: HAL device handle.
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* @msi_cap: MSI Capabilities
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*
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* Return the msi capabilities
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*/
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vxge_hal_status_e
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vxge_hal_mgmt_msi_capabilities_get(vxge_hal_device_h devh,
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vxge_hal_mgmt_msi_cap_t *msi_cap);
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/*
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* vxge_hal_mgmt_msi_capabilities_set - Sets the msi capabilities
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* @devh: HAL device handle.
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* @msi_cap: MSI Capabilities
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*
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* Sets the msi capabilities
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*/
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vxge_hal_status_e
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vxge_hal_mgmt_msi_capabilities_set(vxge_hal_device_h devh,
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vxge_hal_mgmt_msi_cap_t *msi_cap);
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/*
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* struct vxge_hal_mgmt_msix_cap_t - MSIX Capabilities
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* @enable: 1 - MSIX enabled, 0 - MSIX not enabled
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* @mask_all_vect: 1 - Mask all vectors, 0 - Do not mask all vectors
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* @table_size: MSIX Table Size-1
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* @table_offset: Offset of the table from the table_bir
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* @table_bir: Table Bar address register number 0-BAR0, 2-BAR1, 4-BAR2
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* @pba_offset: Offset of the PBA from the pba_bir
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* @pba_bir: PBA Bar address register number 0-BAR0, 2-BAR1, 4-BAR2
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*
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* MSIS Capabilities structure
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*/
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typedef struct vxge_hal_mgmt_msix_cap_t {
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u32 enable;
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u32 mask_all_vect;
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u32 table_size;
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u32 table_offset;
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u32 table_bir;
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#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR0 0
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#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR1 2
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#define VXGE_HAL_MGMT_MSIX_CAP_TABLE_BAR2 4
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u32 pba_offset;
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u32 pba_bir;
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#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR0 0
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#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR1 2
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#define VXGE_HAL_MGMT_MSIX_CAP_PBA_BAR2 4
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} vxge_hal_mgmt_msix_cap_t;
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/*
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* vxge_hal_mgmt_msix_capabilities_get - Returns the msix capabilities
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* @devh: HAL device handle.
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* @msix_cap: MSIX Capabilities
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*
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* Return the msix capabilities
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*/
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vxge_hal_status_e
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vxge_hal_mgmt_msix_capabilities_get(vxge_hal_device_h devh,
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vxge_hal_mgmt_msix_cap_t *msix_cap);
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/*
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* struct vxge_hal_pci_err_cap_t - PCI Error Capabilities
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* @pci_err_header: Error header
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* @pci_err_uncor_status: Uncorrectable error status
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* 0x00000001 - Training
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* 0x00000010 - Data Link Protocol
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* 0x00001000 - Poisoned TLP
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* 0x00002000 - Flow Control Protocol
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* 0x00004000 - Completion Timeout
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* 0x00008000 - Completer Abort
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* 0x00010000 - Unexpected Completion
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* 0x00020000 - Receiver Overflow
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* 0x00040000 - Malformed TLP
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* 0x00080000 - ECRC Error Status
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* 0x00100000 - Unsupported Request
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* @pci_err_uncor_mask: Uncorrectable mask
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* @pci_err_uncor_server: Uncorrectable server
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* @pci_err_cor_status: Correctable status
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* 0x00000001 - Receiver Error Status
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* 0x00000040 - Bad TLP Status
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* 0x00000080 - Bad DLLP Status
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* 0x00000100 - REPLAY_NUM Rollover
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* 0x00001000 - Replay Timer Timeout
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* VXGE_HAL_PCI_ERR_COR_MASK 20
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* @pci_err_cap: Error capability
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* 0x00000020 - ECRC Generation Capable
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* 0x00000040 - ECRC Generation Enable
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* 0x00000080 - ECRC Check Capable
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* 0x00000100 - ECRC Check Enable
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* @err_header_log: Error header log
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* @unused: Reserved
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* @pci_err_root_command: Error root command
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* @pci_err_root_status: Error root status
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* @pci_err_root_cor_src: Error root correctible source
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* @pci_err_root_src: Error root source
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*
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* MSIS Capabilities structure
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*/
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typedef struct vxge_hal_pci_err_cap_t {
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u32 pci_err_header;
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u32 pci_err_uncor_status;
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#define VXGE_HAL_PCI_ERR_CAP_UNC_TRAIN 0x00000001 /* Training */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_DLP 0x00000010 /* Data Link Protocol */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_FCP 0x00002000 /* Flow Ctrl Protocol */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_UNX_COMP 0x00010000 /* Unexpected Compl */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_ECRC 0x00080000 /* ECRC Error Status */
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#define VXGE_HAL_PCI_ERR_CAP_UNC_UNSUP 0x00100000 /* Unsupported Request */
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u32 pci_err_uncor_mask;
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u32 pci_err_uncor_server;
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u32 pci_err_cor_status;
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#define VXGE_HAL_PCI_ERR_CAP_COR_RCVR 0x00000001 /* Recv Err Status */
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#define VXGE_HAL_PCI_ERR_CAP_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
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#define VXGE_HAL_PCI_ERR_CAP_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
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#define VXGE_HAL_PCI_ERR_CAP_COR_REP_ROLL 0x00000100 /* REPLAY Rollover */
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#define VXGE_HAL_PCI_ERR_CAP_COR_REP_TIMER 0x00001000 /* Replay Timeout */
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#define VXGE_HAL_PCI_ERR_CAP_COR_MASK 20 /* Corrble Err Mask */
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u32 pci_err_cap;
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#define VXGE_HAL_PCI_ERR_CAP_CAP_FEP(x) ((x) & 31) /* First Err Ptr */
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#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENC 0x00000020 /* ECRC Gen Capable */
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#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_GENE 0x00000040 /* ECRC Gen Enable */
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#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKC 0x00000080 /* ECRC Chk Capable */
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#define VXGE_HAL_PCI_ERR_CAP_CAP_ECRC_CHKE 0x00000100 /* ECRC Chk Enable */
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u32 err_header_log;
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#define VXGE_HAL_PCI_ERR_CAP_HEADER_LOG(x) ((x) >> 31) /* Error Hdr Log */
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u32 unused[3];
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u32 pci_err_root_command;
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u32 pci_err_root_status;
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u32 pci_err_root_cor_src;
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u32 pci_err_root_src;
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} vxge_hal_pci_err_cap_t;
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/*
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* vxge_hal_mgmt_pci_err_capabilities_get - Returns the pci error capabilities
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* @devh: HAL device handle.
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* @err_cap: PCI-E Extended Error Capabilities
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*
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* Return the PCI-E Extended Error capabilities
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*/
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vxge_hal_status_e
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vxge_hal_mgmt_pci_err_capabilities_get(vxge_hal_device_h devh,
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vxge_hal_pci_err_cap_t *err_cap);
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/*
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* vxge_hal_mgmt_driver_config - Retrieve driver configuration.
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* @drv_config: Device configuration, see vxge_hal_driver_config_t {}.
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* @size: Pointer to buffer containing the Size of the @drv_config.
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* HAL will return an error if the size is smaller than
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* sizeof(vxge_hal_driver_config_t) and returns required size in this field
|
|
*
|
|
* Get driver configuration. Permits to retrieve at run-time configuration
|
|
* values that were used to configure the device at load-time.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - HAL is not initialized.
|
|
* VXGE_HAL_ERR_VERSION_CONFLICT - Version is not maching.
|
|
* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
|
|
*
|
|
* See also: vxge_hal_driver_config_t {}, vxge_hal_mgmt_device_config().
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_driver_config(vxge_hal_driver_config_t *drv_config, u32 *size);
|
|
|
|
#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
|
|
|
|
/*
|
|
* vxge_hal_mgmt_trace_read - Read trace buffer contents.
|
|
* @buffer: Buffer to store the trace buffer contents.
|
|
* @buf_size: Size of the buffer.
|
|
* @offset: Offset in the internal trace buffer to read data.
|
|
* @read_length: Size of the valid data in the buffer.
|
|
*
|
|
* Read HAL trace buffer contents starting from the offset
|
|
* upto the size of the buffer or till EOF is reached.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer.
|
|
*
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_trace_read(char *buffer,
|
|
unsigned buf_size,
|
|
unsigned *offset,
|
|
unsigned *read_length);
|
|
|
|
#endif
|
|
|
|
/*
|
|
* vxge_hal_mgmt_device_config - Retrieve device configuration.
|
|
* @devh: HAL device handle.
|
|
* @dev_config: Device configuration, see vxge_hal_device_config_t {}.
|
|
* @size: Pointer to buffer containing the Size of the @dev_config.
|
|
* HAL will return an error if the size is smaller than
|
|
* sizeof(vxge_hal_device_config_t) and returns required size in this field
|
|
*
|
|
* Get device configuration. Permits to retrieve at run-time configuration
|
|
* values that were used to initialize and configure the device.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
|
|
* VXGE_HAL_ERR_VERSION_CONFLICT - Version it not maching.
|
|
* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
|
|
*
|
|
* See also: vxge_hal_device_config_t {}, vxge_hal_mgmt_driver_config().
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_device_config(vxge_hal_device_h devh,
|
|
vxge_hal_device_config_t *dev_config, u32 *size);
|
|
|
|
|
|
/*
|
|
* vxge_hal_mgmt_pcireg_read - Read PCI configuration at a specified
|
|
* offset.
|
|
* @devh: HAL device handle.
|
|
* @offset: Offset in the 256 byte PCI configuration space.
|
|
* @value_bits: 8, 16, or 32 (bits) to read.
|
|
* @value: Value returned by HAL.
|
|
*
|
|
* Read PCI configuration, given device and offset in the PCI space.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
|
|
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the BAR space is not
|
|
* valid.
|
|
* VXGE_HAL_ERR_INVALID_VALUE_BIT_SIZE - Invalid bits size. Valid
|
|
* values(8/16/32).
|
|
*
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_pcireg_read(vxge_hal_device_h devh, unsigned int offset,
|
|
int value_bits, u32 *value);
|
|
|
|
/*
|
|
* enum vxge_hal_mgmt_reg_type_e - Register types.
|
|
*
|
|
* @vxge_hal_mgmt_reg_type_legacy: Legacy registers
|
|
* @vxge_hal_mgmt_reg_type_toc: TOC Registers
|
|
* @vxge_hal_mgmt_reg_type_common: Common Registers
|
|
* @vxge_hal_mgmt_reg_type_memrepair: Memrepair Registers
|
|
* @vxge_hal_mgmt_reg_type_pcicfgmgmt: pci cfg management registers
|
|
* @vxge_hal_mgmt_reg_type_mrpcim: mrpcim registers
|
|
* @vxge_hal_mgmt_reg_type_srpcim: srpcim registers
|
|
* @vxge_hal_mgmt_reg_type_vpmgmt: vpath management registers
|
|
* @vxge_hal_mgmt_reg_type_vpath: vpath registers
|
|
*
|
|
* Register type enumaration
|
|
*/
|
|
typedef enum vxge_hal_mgmt_reg_type_e {
|
|
vxge_hal_mgmt_reg_type_legacy = 0,
|
|
vxge_hal_mgmt_reg_type_toc = 1,
|
|
vxge_hal_mgmt_reg_type_common = 2,
|
|
vxge_hal_mgmt_reg_type_memrepair = 3,
|
|
vxge_hal_mgmt_reg_type_pcicfgmgmt = 4,
|
|
vxge_hal_mgmt_reg_type_mrpcim = 5,
|
|
vxge_hal_mgmt_reg_type_srpcim = 6,
|
|
vxge_hal_mgmt_reg_type_vpmgmt = 7,
|
|
vxge_hal_mgmt_reg_type_vpath = 8
|
|
} vxge_hal_mgmt_reg_type_e;
|
|
|
|
/*
|
|
* vxge_hal_mgmt_reg_read - Read X3100 register.
|
|
* @devh: HAL device handle.
|
|
* @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
|
|
* @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
|
|
* ignored for others
|
|
* @offset: Register offset in the register space qualified by the type and
|
|
* index.
|
|
* @value: Register value. Returned by HAL.
|
|
* Read X3100 register.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
|
|
* VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
|
|
* VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
|
|
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
|
|
*
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_reg_read(vxge_hal_device_h devh,
|
|
vxge_hal_mgmt_reg_type_e type,
|
|
u32 index,
|
|
u32 offset,
|
|
u64 *value);
|
|
|
|
/*
|
|
* vxge_hal_mgmt_reg_Write - Write X3100 register.
|
|
* @devh: HAL device handle.
|
|
* @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
|
|
* @index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
|
|
* ignored for others
|
|
* @offset: Register offset in the register space qualified by the type and
|
|
* index.
|
|
* @value: Register value to be written.
|
|
* Write X3100 register.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
|
|
* VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
|
|
* VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
|
|
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
|
|
*
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_reg_write(vxge_hal_device_h devh,
|
|
vxge_hal_mgmt_reg_type_e type,
|
|
u32 index,
|
|
u32 offset,
|
|
u64 value);
|
|
|
|
/*
|
|
* vxge_hal_mgmt_bar0_read - Read X3100 register located at the offset
|
|
* from bar0.
|
|
* @devh: HAL device handle.
|
|
* @offset: Register offset from bar0
|
|
* @value: Register value. Returned by HAL.
|
|
* Read X3100 register.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
|
|
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
|
|
*
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_bar0_read(vxge_hal_device_h devh,
|
|
u32 offset,
|
|
u64 *value);
|
|
|
|
/*
|
|
* vxge_hal_mgmt_bar1_read - Read X3100 register located at the offset
|
|
* from bar1.
|
|
* @devh: HAL device handle.
|
|
* @offset: Register offset from bar1
|
|
* @value: Register value. Returned by HAL.
|
|
* Read X3100 register.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
|
|
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
|
|
*
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_bar1_read(vxge_hal_device_h devh,
|
|
u32 offset,
|
|
u64 *value);
|
|
|
|
/*
|
|
* vxge_hal_mgmt_bar0_Write - Write X3100 register located at the offset
|
|
* from bar0.
|
|
* @devh: HAL device handle.
|
|
* @offset: Register offset from bar0
|
|
* @value: Register value to be written.
|
|
* Write X3100 register.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
|
|
* VXGE_HAL_ERR_INVALID_OFFSET - Register offset in the space is not valid.
|
|
*
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_bar0_write(vxge_hal_device_h devh,
|
|
u32 offset,
|
|
u64 value);
|
|
|
|
/*
|
|
* vxge_hal_mgmt_register_config - Retrieve register configuration.
|
|
* @devh: HAL device handle.
|
|
* @type: Register types as defined in enum vxge_hal_mgmt_reg_type_e {}
|
|
* @Index: For pcicfgmgmt, srpcim, vpmgmt, vpath this gives the Index
|
|
* ignored for others
|
|
* @config: Device configuration, see vxge_hal_device_config_t {}.
|
|
* @size: Pointer to buffer containing the Size of the @reg_config.
|
|
* HAL will return an error if the size is smaller than
|
|
* requested register space and returns required size in this field
|
|
*
|
|
* Get register configuration. Permits to retrieve register values.
|
|
*
|
|
* Returns: VXGE_HAL_OK - success.
|
|
* VXGE_HAL_ERR_INVALID_DEVICE - Device is not valid.
|
|
* VXGE_HAL_ERR_INVALID_TYPE - Type is not valid.
|
|
* VXGE_HAL_ERR_INVALID_INDEX - Index is not valid.
|
|
* VXGE_HAL_ERR_OUT_OF_SPACE - If the buffer is not sufficient
|
|
*
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_register_config(vxge_hal_device_h devh,
|
|
vxge_hal_mgmt_reg_type_e type,
|
|
u32 vp_id,
|
|
u8 *config,
|
|
u32 *size);
|
|
|
|
/*
|
|
* vxge_hal_mgmt_read_xfp_current_temp - Read current temparature of given port
|
|
* @devh: HAL device handle.
|
|
* @port: Port number
|
|
*
|
|
* This routine only gets the temperature for XFP modules. Also, updating of the
|
|
* NVRAM can sometimes fail and so the reading we might get may not be uptodate.
|
|
*/
|
|
u32 vxge_hal_mgmt_read_xfp_current_temp(vxge_hal_device_h devh, u32 port);
|
|
|
|
/*
|
|
* vxge_hal_mgmt_pma_loopback - Enable or disable PMA loopback
|
|
* @devh: HAL device handle.
|
|
* @port: Port number
|
|
* @enable:Boolean set to 1 to enable and 0 to disable.
|
|
*
|
|
* Enable or disable PMA loopback.
|
|
* Return value:
|
|
* 0 on success.
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_pma_loopback(vxge_hal_device_h devh, u32 port, u32 enable);
|
|
|
|
/*
|
|
* vxge_hal_mgmt_xgmii_loopback - Enable or disable xgmii loopback
|
|
* @devh: HAL device handle.
|
|
* @port: Port number
|
|
* @enable:Boolean set to 1 to enable and 0 to disable.
|
|
*
|
|
* Enable or disable xgmii loopback.
|
|
* Return value:
|
|
* 0 on success.
|
|
*/
|
|
vxge_hal_status_e
|
|
vxge_hal_mgmt_xgmii_loopback(vxge_hal_device_h devh, u32 port, u32 enable);
|
|
|
|
__EXTERN_END_DECLS
|
|
|
|
#endif /* VXGE_HAL_MGMT_H */
|