60e575821e
The old code was spread out through the machdep code and was sloppy about enabling and disabling the FEN bit (which controls access to the FP register set). This caused a DIAGNOSTIC warning "DANGER WILL ROBINSON: FEN SET IN cpu_fork!" sometimes when operating under high loads and could conceivably lead to processes getting incorrect FP results. The new code is much more strict about the FEN bit and makes sure that *only* fpcurproc ever has it enabled. This also allows us to remove a section of code from the exception_return path which might improve performance marginally. Reviewed by: gallatin
410 lines
11 KiB
C
410 lines
11 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sysproto.h>
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#include <sys/sysent.h>
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#include <sys/proc.h>
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#include <sys/lock.h>
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#include <vm/vm.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_page.h>
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#include <vm/vm_map.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_object.h>
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#include <vm/vm_pager.h>
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#include <sys/user.h>
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#include <machine/inst.h>
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#include <machine/fpu.h>
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#include <machine/reg.h>
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#include <alpha/alpha/ieee_float.h>
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#define GETREG(regs, i) (*(fp_register_t*) ®s->fpr_regs[i])
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#define PUTREG(regs, i, v) (*(fp_register_t*) ®s->fpr_regs[i] = v)
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typedef fp_register_t fp_opcode_handler(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t fp_control,
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u_int64_t *status,
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struct fpreg *fpregs);
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static fp_register_t fp_add(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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return ieee_add(GETREG(fpregs, ins.f_format.fa),
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GETREG(fpregs, ins.f_format.fb),
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src, rnd, control, status);
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}
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static fp_register_t fp_sub(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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return ieee_sub(GETREG(fpregs, ins.f_format.fa),
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GETREG(fpregs, ins.f_format.fb),
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src, rnd, control, status);
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}
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static fp_register_t fp_mul(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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return ieee_mul(GETREG(fpregs, ins.f_format.fa),
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GETREG(fpregs, ins.f_format.fb),
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src, rnd, control, status);
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}
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static fp_register_t fp_div(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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return ieee_div(GETREG(fpregs, ins.f_format.fa),
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GETREG(fpregs, ins.f_format.fb),
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src, rnd, control, status);
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}
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static fp_register_t fp_cmpun(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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return ieee_cmpun(GETREG(fpregs, ins.f_format.fa),
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GETREG(fpregs, ins.f_format.fb),
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status);
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}
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static fp_register_t fp_cmpeq(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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return ieee_cmpeq(GETREG(fpregs, ins.f_format.fa),
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GETREG(fpregs, ins.f_format.fb),
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status);
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}
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static fp_register_t fp_cmplt(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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return ieee_cmplt(GETREG(fpregs, ins.f_format.fa),
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GETREG(fpregs, ins.f_format.fb),
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status);
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}
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static fp_register_t fp_cmple(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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return ieee_cmple(GETREG(fpregs, ins.f_format.fa),
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GETREG(fpregs, ins.f_format.fb),
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status);
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}
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static fp_register_t fp_cvts(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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switch (src) {
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case T_FORMAT:
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return ieee_convert_T_S(GETREG(fpregs, ins.f_format.fb),
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rnd, control, status);
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case Q_FORMAT:
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return ieee_convert_Q_S(GETREG(fpregs, ins.f_format.fb),
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rnd, control, status);
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default:
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*status |= FPCR_INV;
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return GETREG(fpregs, ins.f_format.fc);
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}
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}
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static fp_register_t fp_cvtt(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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switch (src) {
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case S_FORMAT:
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return ieee_convert_S_T(GETREG(fpregs, ins.f_format.fb),
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rnd, control, status);
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break;
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case Q_FORMAT:
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return ieee_convert_Q_T(GETREG(fpregs, ins.f_format.fb),
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rnd, control, status);
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break;
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default:
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*status |= FPCR_INV;
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return GETREG(fpregs, ins.f_format.fc);
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}
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}
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static fp_register_t fp_cvtq(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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switch (src) {
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case S_FORMAT:
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return ieee_convert_S_Q(GETREG(fpregs, ins.f_format.fb),
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rnd, control, status);
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break;
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case T_FORMAT:
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return ieee_convert_T_Q(GETREG(fpregs, ins.f_format.fb),
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rnd, control, status);
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break;
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default:
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*status |= FPCR_INV;
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return GETREG(fpregs, ins.f_format.fc);
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}
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}
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static fp_register_t fp_reserved(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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*status |= FPCR_INV;
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return GETREG(fpregs, ins.f_format.fc);
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}
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static fp_register_t fp_cvtql(union alpha_instruction ins,
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int src, int rnd,
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u_int64_t control, u_int64_t *status,
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struct fpreg *fpregs)
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{
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fp_register_t fb = GETREG(fpregs, ins.f_format.fb);
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fp_register_t ret;
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*status |= FPCR_INV;
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ret.q = ((fb.q & 0xc0000000) << 32 | (fb.q & 0x3fffffff) << 29);
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return ret;
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}
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static int fp_emulate(union alpha_instruction ins, struct proc *p)
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{
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u_int64_t control = p->p_addr->u_pcb.pcb_fp_control;
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struct fpreg *fpregs = &p->p_addr->u_pcb.pcb_fp;
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static fp_opcode_handler *ops[16] = {
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fp_add, /* 0 */
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fp_sub, /* 1 */
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fp_mul, /* 2 */
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fp_div, /* 3 */
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fp_cmpun, /* 4 */
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fp_cmpeq, /* 5 */
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fp_cmplt, /* 6 */
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fp_cmple, /* 7 */
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fp_reserved, /* 8 */
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fp_reserved, /* 9 */
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fp_reserved, /* 10 */
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fp_reserved, /* 11 */
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fp_cvts, /* 12 */
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fp_reserved, /* 13 */
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fp_cvtt, /* 14 */
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fp_cvtq, /* 15 */
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};
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int src, rnd;
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fp_register_t result;
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u_int64_t status;
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/*
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* Only attempt to emulate ieee instructions & integer overflow
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*/
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if ((ins.common.opcode != op_flti) &&
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(ins.f_format.function != fltl_cvtqlsv)){
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printf("fp_emulate: unhandled opcode = 0x%x, fun = 0x%x\n",ins.common.opcode,ins.f_format.function);
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return 0;
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}
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/*
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* Dump the float registers into the pcb so we can get at
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* them. We are potentially going to modify the fp state, so
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* cancel fpcurproc too.
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*/
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alpha_fpstate_save(p, 1);
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/*
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* Decode and execute the instruction.
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*/
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src = (ins.f_format.function >> 4) & 3;
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rnd = (ins.f_format.function >> 6) & 3;
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if (rnd == 3)
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rnd = (fpregs->fpr_cr >> FPCR_DYN_SHIFT) & 3;
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status = 0;
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if (ins.common.opcode == op_fltl
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&& ins.f_format.function == fltl_cvtqlsv)
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result = fp_cvtql(ins, src, rnd, control, &status,
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fpregs);
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else
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result = ops[ins.f_format.function & 0xf](ins, src, rnd,
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control, &status,
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fpregs);
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/*
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* Handle exceptions.
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*/
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if (status) {
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u_int64_t fpcr;
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/* Record the exception in the software control word. */
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control |= (status >> IEEE_STATUS_TO_FPCR_SHIFT);
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p->p_addr->u_pcb.pcb_fp_control = control;
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/* Regenerate the control register */
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fpcr = fpregs->fpr_cr & FPCR_DYN_MASK;
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fpcr |= ((control & IEEE_STATUS_MASK)
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<< IEEE_STATUS_TO_FPCR_SHIFT);
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if (!(control & IEEE_TRAP_ENABLE_INV))
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fpcr |= FPCR_INVD;
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if (!(control & IEEE_TRAP_ENABLE_DZE))
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fpcr |= FPCR_DZED;
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if (!(control & IEEE_TRAP_ENABLE_OVF))
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fpcr |= FPCR_OVFD;
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if (!(control & IEEE_TRAP_ENABLE_UNF))
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fpcr |= FPCR_UNFD;
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if (!(control & IEEE_TRAP_ENABLE_INE))
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fpcr |= FPCR_INED;
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if (control & IEEE_STATUS_MASK)
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fpcr |= FPCR_SUM;
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fpregs->fpr_cr = fpcr;
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/* Check the trap enable */
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if ((control >> IEEE_STATUS_TO_EXCSUM_SHIFT)
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& (control & IEEE_TRAP_ENABLE_MASK))
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return 0;
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}
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PUTREG(fpregs, ins.f_format.fc, result);
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return 1;
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}
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/*
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* Attempt to complete a floating point instruction which trapped by
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* emulating it in software. Return non-zero if the completion was
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* successful, otherwise zero.
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*/
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int fp_software_completion(u_int64_t regmask, struct proc *p)
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{
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struct trapframe *frame = p->p_md.md_tf;
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u_int64_t pc = frame->tf_regs[FRAME_PC];
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int error;
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/*
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* First we must search back through the trap shadow to find which
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* instruction was responsible for generating the trap.
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*/
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pc -= 4;
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while (regmask) {
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union alpha_instruction ins;
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/*
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* Read the instruction and figure out the destination
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* register and opcode.
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*/
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error = copyin((caddr_t) pc, &ins, sizeof(ins));
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if (error)
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return 0;
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switch (ins.common.opcode) {
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case op_call_pal:
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case op_jsr:
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case op_br ... op_bgt:
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/*
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* Condition 6: the trap shadow may not
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* include any branch instructions. Also,
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* the trap shadow is bounded by EXCB, TRAPB
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* and CALL_PAL.
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*/
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return 0;
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case op_misc:
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switch (ins.memory_format.function) {
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case misc_trapb:
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case misc_excb:
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return 0;
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}
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break;
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case op_inta:
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case op_intl:
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case op_ints:
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/*
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* The first 32 bits of the register mask
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* represents integer registers which were
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* modified in the trap shadow.
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*/
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regmask &= ~(1LL << ins.o_format.rc);
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break;
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case op_fltv:
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case op_flti:
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case op_fltl:
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/*
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* The second 32 bits of the register mask
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* represents float registers which were
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* modified in the trap shadow.
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*/
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regmask &= ~(1LL << (ins.f_format.fc + 32));
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break;
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}
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if (regmask == 0) {
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/*
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* We have traced back through all the
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* instructions in the trap shadow, so this
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* must be the one which generated the trap.
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*/
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if (fp_emulate(ins, p)) {
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/*
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* Restore pc to the first instruction
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* in the trap shadow.
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*/
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frame->tf_regs[FRAME_PC] = pc + 4;
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return 1;
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} else
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return 0;
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}
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pc -= 4;
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}
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return 0;
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}
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