22c7a03178
TDMA and CESA registers are placed in different ranges of memory. Split memory resource in DTS to reflect that. This change is needed to support multiple CESA nodes as otherwise the ranges of different nodes would overlap. In consequence, CESA_WRITE and CESA_READ macros have been split depending on which range of registers is accessed. Offsets for CESA registers have been modified as the base address has changed. Submitted by: Michal Stanek <mst@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D6217
333 lines
7.7 KiB
Plaintext
333 lines
7.7 KiB
Plaintext
/*
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* Copyright (c) 2010 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under sponsorship from
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* the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Marvell DB-78100 Device Tree Source.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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/ {
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model = "mrvl,DB-78100";
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compatible = "DB-78100-BP", "DB-78100-BP-A";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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serial0 = &serial0;
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serial1 = &serial1;
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mpp = &MPP;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "ARM,88FR571";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x4000>; // L1, 16K
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i-cache-size = <0x4000>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x20000000>; // 512M at 0x0
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};
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localbus@0 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "mrvl,lbc";
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bank-count = <5>;
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/* This reflects CPU decode windows setup. */
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ranges = <0x0 0x2f 0xf9300000 0x00100000
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0x1 0x3e 0xf9400000 0x00100000
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0x2 0x3d 0xf9500000 0x02000000
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0x3 0x3b 0xfb500000 0x00100000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x00100000>;
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};
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led@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "led";
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reg = <0x1 0x0 0x00100000>;
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};
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nor@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x2 0x0 0x02000000>;
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};
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nand@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mrvl,nfc";
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reg = <0x3 0x0 0x00100000>;
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};
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};
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soc78100@f1000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0xf1000000 0x00100000>;
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bus-frequency = <0>;
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PIC: pic@20200 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x20200 0x3c>;
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compatible = "mrvl,pic";
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};
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timer@20300 {
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compatible = "mrvl,timer";
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reg = <0x20300 0x30>;
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interrupts = <8>;
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interrupt-parent = <&PIC>;
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mrvl,has-wdt;
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};
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MPP: mpp@10000 {
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#pin-cells = <2>;
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compatible = "mrvl,mpp";
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reg = <0x10000 0x34>;
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pin-count = <50>;
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pin-map = <
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0 2 /* MPP[0]: GE1_TXCLK */
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1 2 /* MPP[1]: GE1_TXCTL */
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2 2 /* MPP[2]: GE1_RXCTL */
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3 2 /* MPP[3]: GE1_RXCLK */
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4 2 /* MPP[4]: GE1_TXD[0] */
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5 2 /* MPP[5]: GE1_TXD[1] */
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6 2 /* MPP[6]: GE1_TXD[2] */
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7 2 /* MPP[7]: GE1_TXD[3] */
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8 2 /* MPP[8]: GE1_RXD[0] */
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9 2 /* MPP[9]: GE1_RXD[1] */
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10 2 /* MPP[10]: GE1_RXD[2] */
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11 2 /* MPP[11]: GE1_RXD[3] */
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13 3 /* MPP[13]: SYSRST_OUTn */
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14 3 /* MPP[14]: SATA1_ACTn */
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15 3 /* MPP[15]: SATA0_ACTn */
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16 4 /* MPP[16]: UA2_TXD */
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17 4 /* MPP[17]: UA2_RXD */
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18 3 /* MPP[18]: <UNKNOWN> */
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19 3 /* MPP[19]: <UNKNOWN> */
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20 3 /* MPP[20]: <UNKNOWN> */
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21 3 /* MPP[21]: <UNKNOWN> */
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22 4 /* MPP[22]: UA3_TXD */
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23 4 >; /* MPP[21]: UA3_RXD */
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};
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GPIO: gpio@10100 {
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#gpio-cells = <3>;
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compatible = "mrvl,gpio";
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reg = <0x10100 0x20>;
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gpio-controller;
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interrupts = <56 57 58 59>;
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interrupt-parent = <&PIC>;
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};
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rtc@10300 {
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compatible = "mrvl,rtc";
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reg = <0x10300 0x08>;
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};
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twsi@11000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,twsi";
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reg = <0x11000 0x20>;
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interrupts = <2>;
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interrupt-parent = <&PIC>;
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};
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twsi@11100 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,twsi";
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reg = <0x11100 0x20>;
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interrupts = <3>;
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interrupt-parent = <&PIC>;
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};
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enet0: ethernet@72000 {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "V2";
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compatible = "mrvl,ge";
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reg = <0x72000 0x2000>;
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ranges = <0x0 0x72000 0x2000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <41 42 43 40 70>;
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interrupt-parent = <&PIC>;
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phy-handle = <&phy0>;
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,mdio";
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phy0: ethernet-phy@0 {
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reg = <0x8>;
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};
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phy1: ethernet-phy@1 {
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reg = <0x9>;
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};
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};
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};
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enet1: ethernet@76000 {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "V2";
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compatible = "mrvl,ge";
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reg = <0x76000 0x2000>;
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ranges = <0x0 0x76000 0x2000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <45 46 47 44 70>;
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interrupt-parent = <&PIC>;
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phy-handle = <&phy1>;
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};
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serial0: serial@12000 {
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compatible = "ns16550";
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reg = <0x12000 0x20>;
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reg-shift = <2>;
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clock-frequency = <0>;
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interrupts = <12>;
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interrupt-parent = <&PIC>;
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};
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serial1: serial@12100 {
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compatible = "ns16550";
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reg = <0x12100 0x20>;
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reg-shift = <2>;
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clock-frequency = <0>;
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interrupts = <13>;
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interrupt-parent = <&PIC>;
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};
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usb@50000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x50000 0x1000>;
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interrupts = <72 16>;
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interrupt-parent = <&PIC>;
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};
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usb@51000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x51000 0x1000>;
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interrupts = <72 17>;
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interrupt-parent = <&PIC>;
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};
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usb@52000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x52000 0x1000>;
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interrupts = <72 18>;
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interrupt-parent = <&PIC>;
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};
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xor@60000 {
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compatible = "mrvl,xor";
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reg = <0x60000 0x1000>;
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interrupts = <22 23>;
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interrupt-parent = <&PIC>;
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};
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crypto@90000 {
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compatible = "mrvl,cesa";
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reg = <0x90000 0x1000 /* tdma base reg chan 0 */
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0x9D000 0x1000>; /* cesa base reg chan 0 */
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interrupts = <19>;
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interrupt-parent = <&PIC>;
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};
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sata@a0000 {
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compatible = "mrvl,sata";
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reg = <0xa0000 0x6000>;
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interrupts = <26>;
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interrupt-parent = <&PIC>;
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};
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};
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pci0: pcie@f1040000 {
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compatible = "mrvl,pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xf1040000 0x2000>;
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bus-range = <0 255>;
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ranges = <0x02000000 0x0 0xf2000000 0xf2000000 0x0 0x04000000
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0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&PIC>;
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interrupts = <68>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x1 */
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0x0800 0x0 0x0 0x1 &PIC 0x20
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0x0800 0x0 0x0 0x2 &PIC 0x21
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0x0800 0x0 0x0 0x3 &PIC 0x22
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0x0800 0x0 0x0 0x4 &PIC 0x23
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>;
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};
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sram@fd000000 {
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compatible = "mrvl,cesa-sram";
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reg = <0xfd000000 0x00100000>;
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};
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chosen {
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stdin = "serial0";
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stdout = "serial0";
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};
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};
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