ca8e20784a
After ARM_INTRNG introduction, MPIC code needed several modifications: - IRQ resource and its handler added - several DEVMETHODs of INTRNG interface implemented - defines enhanced to ensure code compiles as well for AXP as for A38X - added dummy MSI_IRQ, ERR_IRQ defines for Armada38x - MPIC driver was added to files.armada38x, ARM_INTRNG option enabled in kernconf file and regs of MPIC corrected in dts file. Instead of modifying Armada38X DTS, offsets to CPU registers defined in driver were changed. That required restoring 'reg' property of mpic node in ArmadaXP to state compliant with Linux DTS. Additionally, required ARM_INTRNG definitions were added to mv_common.c. Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: adrian, andrew, ian, skra Approved by: cognet (mentor) Differential Revision: https://reviews.freebsd.org/D5030
324 lines
7.0 KiB
Plaintext
324 lines
7.0 KiB
Plaintext
/*
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* Copyright (c) 2010 The FreeBSD Foundation
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* Copyright (c) 2010-2011 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Marvell DB-78460 Device Tree Source.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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/ {
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model = "mrvl,DB-78460";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "ARM,88VS584";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <200000000>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x80000000>; // 2G at 0x0
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};
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soc78460@d0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0xd0000000 0x00100000>;
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bus-frequency = <0>;
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MPIC: mpic@20a00 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x20a00 0x500 0x21870 0x58 0x20400 0x100>;
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compatible = "mrvl,mpic";
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};
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rtc@10300 {
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compatible = "mrvl,rtc";
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reg = <0x10300 0x08>;
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};
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timer@21840 {
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compatible = "mrvl,timer";
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reg = <0x21840 0x30>;
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interrupts = <5>;
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interrupt-parent = <&MPIC>;
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mrvl,has-wdt;
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};
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twsi@11000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,twsi";
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reg = <0x11000 0x20>;
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interrupts = <31>;
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interrupt-parent = <&MPIC>;
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};
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twsi@11100 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,twsi";
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reg = <0x11100 0x20>;
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interrupts = <32>;
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interrupt-parent = <&MPIC>;
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};
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serial0: serial@12000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x20>;
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reg-shift = <2>;
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current-speed = <115200>;
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clock-frequency = <0>;
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interrupts = <41>;
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interrupt-parent = <&MPIC>;
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};
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serial1: serial@12100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12100 0x20>;
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reg-shift = <2>;
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current-speed = <115200>;
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clock-frequency = <0>;
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interrupts = <42>;
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interrupt-parent = <&MPIC>;
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};
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serial2: serial@12200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12200 0x20>;
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reg-shift = <2>;
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current-speed = <115200>;
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clock-frequency = <0>;
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interrupts = <43>;
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interrupt-parent = <&MPIC>;
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};
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serial3: serial@12300 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12300 0x20>;
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reg-shift = <2>;
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current-speed = <115200>;
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clock-frequency = <0>;
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interrupts = <44>;
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interrupt-parent = <&MPIC>;
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};
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MPP: mpp@10000 {
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#pin-cells = <2>;
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compatible = "mrvl,mpp";
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reg = <0x18000 0x34>;
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pin-count = <68>;
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pin-map = <
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0 1 /* MPP[0]: GE1_TXCLK */
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1 1 /* MPP[1]: GE1_TXCTL */
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2 1 /* MPP[2]: GE1_RXCTL */
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3 1 /* MPP[3]: GE1_RXCLK */
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4 1 /* MPP[4]: GE1_TXD[0] */
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5 1 /* MPP[5]: GE1_TXD[1] */
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6 1 /* MPP[6]: GE1_TXD[2] */
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7 1 /* MPP[7]: GE1_TXD[3] */
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8 1 /* MPP[8]: GE1_RXD[0] */
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9 1 /* MPP[9]: GE1_RXD[1] */
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10 1 /* MPP[10]: GE1_RXD[2] */
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11 1 /* MPP[11]: GE1_RXD[3] */
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12 2 /* MPP[13]: SYSRST_OUTn */
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13 2 /* MPP[13]: SYSRST_OUTn */
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14 2 /* MPP[14]: SATA1_ACTn */
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15 2 /* MPP[15]: SATA0_ACTn */
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16 2 /* MPP[16]: UA2_TXD */
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17 2 /* MPP[17]: UA2_RXD */
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18 2 /* MPP[18]: <UNKNOWN> */
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19 2 /* MPP[19]: <UNKNOWN> */
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20 2 /* MPP[20]: <UNKNOWN> */
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21 2 /* MPP[21]: <UNKNOWN> */
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22 2 /* MPP[22]: UA3_TXD */
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23 2
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24 0
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25 0
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26 0
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27 0
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28 4
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29 0
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30 1
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31 1
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32 1
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33 1
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34 1
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35 1
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36 1
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37 1
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38 1
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39 1
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40 0
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41 3
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42 1
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43 1
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44 2
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45 2
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46 4
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47 3
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48 0
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49 1
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50 1
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51 1
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52 1
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53 1
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54 1
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55 1
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56 1
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57 0
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58 1
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59 1
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60 1
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61 1
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62 1
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63 1
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64 1
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65 1
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66 1
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67 2 >;
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};
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usb@50000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x50000 0x1000>;
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interrupts = <124 45>;
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interrupt-parent = <&MPIC>;
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};
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usb@51000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x51000 0x1000>;
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interrupts = <124 46>;
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interrupt-parent = <&MPIC>;
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};
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usb@52000 {
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compatible = "mrvl,usb-ehci", "usb-ehci";
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reg = <0x52000 0x1000>;
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interrupts = <124 47>;
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interrupt-parent = <&MPIC>;
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};
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enet0: ethernet@72000 {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "V2";
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compatible = "mrvl,ge";
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reg = <0x72000 0x2000>;
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ranges = <0x0 0x72000 0x2000>;
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local-mac-address = [ 00 04 01 07 84 60 ];
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interrupts = <67 68 122 >;
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interrupt-parent = <&MPIC>;
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phy-handle = <&phy0>;
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has-neta;
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mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mrvl,mdio";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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};
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phy2: ethernet-phy@2 {
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reg = <0x19>;
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};
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phy3: ethernet-phy@3 {
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reg = <0x1b>;
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};
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};
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};
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sata@A0000 {
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compatible = "mrvl,sata";
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reg = <0xA0000 0x6000>;
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interrupts = <55>;
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interrupt-parent = <&MPIC>;
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};
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};
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pci0: pcie@d0040000 {
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compatible = "mrvl,pcie";
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xd0040000 0x2000>;
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bus-range = <0 255>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xa0000000 0x0 0x08000000>;
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clock-frequency = <33333333>;
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interrupt-parent = <&MPIC>;
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interrupts = <120>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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0x0800 0x0 0x0 0x1 &MPIC 0x3A
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0x0800 0x0 0x0 0x2 &MPIC 0x3A
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0x0800 0x0 0x0 0x3 &MPIC 0x3A
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0x0800 0x0 0x0 0x4 &MPIC 0x3A
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>;
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};
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sram@ffff0000 {
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compatible = "mrvl,cesa-sram";
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reg = <0xffff0000 0x00010000>;
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};
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chosen {
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stdin = "serial0";
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stdout = "serial0";
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stddbg = "serial0";
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};
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};
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