9862cef040
RISC-V cpu implementations. o Update RocketChip device tree source (DTS). We now support latest verison of RocketChip synthesized on Xilinx FPGA (Zedboard). RocketChip is an implementation of RISC-V processor written on Chisel hardware construction language. Sponsored by: DARPA, AFRL Sponsored by: HEIF5
106 lines
2.9 KiB
Plaintext
106 lines
2.9 KiB
Plaintext
/*-
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* Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* Portions of this software were developed by SRI International and the
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* University of Cambridge Computer Laboratory under DARPA/AFRL contract
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* FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Portions of this software were developed by the University of Cambridge
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* Computer Laboratory as part of the CTSRD Project, with support from the
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* UK Higher Education Innovation Fund (HEIF).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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/ {
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model = "RocketChip RV64";
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compatible = "riscv,rv64";
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "riscv,rv64";
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reg = <0x0>;
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};
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};
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aliases {
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console0 = &console0;
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};
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memory {
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/*
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* This is not used currently.
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* We take information from sbi_query_memory.
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*/
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256MB at 0x80000000 */
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <1>;
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compatible = "simple-bus";
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ranges;
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pic0: pic@0 {
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compatible = "riscv,pic";
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interrupt-controller;
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};
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timer0: timer@0 {
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compatible = "riscv,timer";
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reg = < 0x4400bff8 0x0008 >, /* rtc */
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< 0x44004000 0x1000 >; /* timecmp */
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interrupts = < 5 >;
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interrupt-parent = < &pic0 >;
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clock-frequency = < 1000000 >;
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};
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console0: console@0 {
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compatible = "riscv,console";
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status = "okay";
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interrupts = < 1 >;
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interrupt-parent = < &pic0 >;
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};
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};
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chosen {
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bootargs = "-v";
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stdin = "console0";
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stdout = "console0";
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};
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};
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