718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
250 lines
8.5 KiB
C
250 lines
8.5 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/**
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* @file
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*
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* @brief This file contains the method implementations utilized in writing
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* out PCI data for the SCI core.
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*/
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#include <dev/isci/scil/scic_user_callback.h>
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#include <dev/isci/scil/scic_sds_pci.h>
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#include <dev/isci/scil/scic_sds_controller.h>
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/**
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* @brief This method reads from the driver the BARs that are needed to
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* determine the virtual memory space for the controller registers
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*
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* @param[in] this_controller The controller for which to read the base
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* address registers.
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*/
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void scic_sds_pci_bar_initialization(
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SCIC_SDS_CONTROLLER_T* this_controller
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)
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{
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#ifdef ARLINGTON_BUILD
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#define ARLINGTON_LEX_BAR 0
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#define ARLINGTON_SMU_BAR 1
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#define ARLINGTON_SCU_BAR 2
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#define LEX_REGISTER_OFFSET 0x40000
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this_controller->lex_registers =
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((char *)scic_cb_pci_get_bar(
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this_controller, ARLINGTON_LEX_BAR) + LEX_REGISTER_OFFSET);
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this_controller->smu_registers =
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(SMU_REGISTERS_T *)scic_cb_pci_get_bar(this_controller, ARLINGTON_SMU_BAR);
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this_controller->scu_registers =
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(SCU_REGISTERS_T *)scic_cb_pci_get_bar(this_controller, ARLINGTON_SCU_BAR);
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#else // !ARLINGTON_BUILD
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#if !defined(ENABLE_PCI_IO_SPACE_ACCESS)
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this_controller->smu_registers =
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(SMU_REGISTERS_T *)(
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(char *)scic_cb_pci_get_bar(this_controller, PATSBURG_SMU_BAR)
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+(0x4000 * this_controller->controller_index));
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this_controller->scu_registers =
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(SCU_REGISTERS_T *)(
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(char *)scic_cb_pci_get_bar(this_controller, PATSBURG_SCU_BAR)
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+(0x400000 * this_controller->controller_index));
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#else // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
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if (this_controller->controller_index == 0)
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{
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this_controller->smu_registers = (SMU_REGISTERS_T *)
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scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR0);
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}
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else
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{
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if (this_controller->pci_revision == SCU_PBG_HBA_REV_B0)
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{
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// SCU B0 violates PCI spec for size of IO bar this is corrected
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// in subsequent version of the hardware so we can safely use the
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// else condition below.
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this_controller->smu_registers = (SMU_REGISTERS_T *)
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(scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR0) + 0x100);
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}
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else
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{
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this_controller->smu_registers = (SMU_REGISTERS_T *)
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scic_cb_pci_get_bar(this_controller, PATSBURG_IO_SPACE_BAR1);
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}
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}
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// No need to get the bar. We will be using the offset to write to
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// input/output ports via 0xA0 and 0xA4.
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this_controller->scu_registers = (SCU_REGISTERS_T *) 0;
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#endif // !defined(ENABLE_PCI_IO_SPACE_ACCESS)
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#endif // ARLINGTON_BUILD
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}
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#if defined(ENABLE_PCI_IO_SPACE_ACCESS) && !defined(ARLINGTON_BUILD)
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/**
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* @brief This method will read from PCI memory for the SMU register
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* space via IO space access.
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*
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* @param[in] controller The controller for which to read a DWORD.
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* @param[in] address This parameter depicts the address from
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* which to read.
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*
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* @return The value being returned from the PCI memory location.
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*
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* @todo This PCI memory access calls likely need to be optimized into macro?
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*/
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U32 scic_sds_pci_read_smu_dword(
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SCI_CONTROLLER_HANDLE_T controller,
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void * address
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)
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{
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return scic_cb_pci_read_dword(controller, address);
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}
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/**
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* @brief This method will write to PCI memory for the SMU register
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* space via IO space access.
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*
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* @param[in] controller The controller for which to read a DWORD.
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* @param[in] address This parameter depicts the address into
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* which to write.
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* @param[out] write_value This parameter depicts the value being written
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* into the PCI memory location.
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*
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* @todo This PCI memory access calls likely need to be optimized into macro?
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*/
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void scic_sds_pci_write_smu_dword(
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SCI_CONTROLLER_HANDLE_T controller,
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void * address,
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U32 write_value
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)
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{
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scic_cb_pci_write_dword(controller, address, write_value);
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}
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/**
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* @brief This method will read from PCI memory for the SCU register
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* space via IO space access.
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*
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* @param[in] controller The controller for which to read a DWORD.
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* @param[in] address This parameter depicts the address from
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* which to read.
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*
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* @return The value being returned from the PCI memory location.
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*
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* @todo This PCI memory access calls likely need to be optimized into macro?
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*/
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U32 scic_sds_pci_read_scu_dword(
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SCI_CONTROLLER_HANDLE_T controller,
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void * address
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)
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{
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SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
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scic_cb_pci_write_dword(
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controller,
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(void*) ((char *)(this_controller->smu_registers) + SCU_MMR_ADDRESS_WINDOW_OFFSET),
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(U32) address
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);
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return scic_cb_pci_read_dword(
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controller,
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(void*) ((char *)(this_controller->smu_registers) + SCU_MMR_DATA_WINDOW_OFFSET)
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);
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}
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/**
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* @brief This method will write to PCI memory for the SCU register
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* space via IO space access.
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*
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* @param[in] controller The controller for which to read a DWORD.
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* @param[in] address This parameter depicts the address into
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* which to write.
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* @param[out] write_value This parameter depicts the value being written
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* into the PCI memory location.
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*
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* @todo This PCI memory access calls likely need to be optimized into macro?
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*/
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void scic_sds_pci_write_scu_dword(
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SCI_CONTROLLER_HANDLE_T controller,
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void * address,
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U32 write_value
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)
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{
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SCIC_SDS_CONTROLLER_T * this_controller = (SCIC_SDS_CONTROLLER_T*)controller;
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scic_cb_pci_write_dword(
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controller,
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(void*) ((char *)(this_controller->smu_registers) + SCU_MMR_ADDRESS_WINDOW_OFFSET),
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(U32) address
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);
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scic_cb_pci_write_dword(
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controller,
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(void*) ((char *)(this_controller->smu_registers) + SCU_MMR_DATA_WINDOW_OFFSET),
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write_value
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);
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}
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#endif // defined(ENABLE_PCI_IO_SPACE_ACCESS)
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