6e32690075
caches if not yet enabed. This is required for coherency and atomic operations to work, not to mention performance. We use the L2 and L3 cache settings of the BSP to configure the APs caches. Can't be bad. Program NAP and not DOZE. DOZE is present only on earlier CPUs and the bit is reserved on the MPC7441 & MPC7451. NAP will do bus snooping to keep caches coherent. Program the PIR with the cpuid. This may not be necessary...
299 lines
6.1 KiB
C
299 lines
6.1 KiB
C
/*-
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* Copyright (c) 2008 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <machine/bat.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/hid.h>
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#include <machine/intr_machdep.h>
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#include <machine/pcb.h>
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#include <machine/psl.h>
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#include <machine/smp.h>
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#include <machine/spr.h>
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#include <machine/trap_aim.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/ofw_machdep.h>
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extern void *rstcode;
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extern register_t l2cr_config;
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extern register_t l3cr_config;
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void *ap_pcpu;
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static int
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powerpc_smp_fill_cpuref(struct cpuref *cpuref, phandle_t cpu)
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{
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int cpuid, res;
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cpuref->cr_hwref = cpu;
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res = OF_getprop(cpu, "reg", &cpuid, sizeof(cpuid));
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if (res < 0)
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return (ENOENT);
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cpuref->cr_cpuid = cpuid & 0xff;
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return (0);
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}
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int
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powerpc_smp_first_cpu(struct cpuref *cpuref)
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{
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char buf[8];
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phandle_t cpu, dev, root;
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int res;
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root = OF_peer(0);
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dev = OF_child(root);
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while (dev != 0) {
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res = OF_getprop(dev, "name", buf, sizeof(buf));
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if (res > 0 && strcmp(buf, "cpus") == 0)
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break;
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dev = OF_peer(dev);
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}
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if (dev == 0)
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return (ENOENT);
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cpu = OF_child(dev);
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while (cpu != 0) {
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res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
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if (res > 0 && strcmp(buf, "cpu") == 0)
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break;
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cpu = OF_peer(cpu);
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}
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if (cpu == 0)
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return (ENOENT);
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return (powerpc_smp_fill_cpuref(cpuref, cpu));
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}
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int
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powerpc_smp_next_cpu(struct cpuref *cpuref)
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{
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char buf[8];
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phandle_t cpu;
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int res;
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cpu = OF_peer(cpuref->cr_hwref);
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while (cpu != 0) {
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res = OF_getprop(cpu, "device_type", buf, sizeof(buf));
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if (res > 0 && strcmp(buf, "cpu") == 0)
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break;
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cpu = OF_peer(cpu);
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}
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if (cpu == 0)
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return (ENOENT);
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return (powerpc_smp_fill_cpuref(cpuref, cpu));
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}
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int
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powerpc_smp_get_bsp(struct cpuref *cpuref)
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{
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ihandle_t inst;
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phandle_t bsp, chosen;
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int res;
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chosen = OF_finddevice("/chosen");
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if (chosen == 0)
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return (ENXIO);
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res = OF_getprop(chosen, "cpu", &inst, sizeof(inst));
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if (res < 0)
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return (ENXIO);
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bsp = OF_instance_to_package(inst);
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return (powerpc_smp_fill_cpuref(cpuref, bsp));
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}
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static register_t
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l2_enable(void)
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{
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register_t ccr;
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ccr = mfspr(SPR_L2CR);
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if (ccr & L2CR_L2E)
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return (ccr);
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/* Configure L2 cache. */
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ccr = l2cr_config & ~L2CR_L2E;
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mtspr(SPR_L2CR, ccr | L2CR_L2I);
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do {
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ccr = mfspr(SPR_L2CR);
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} while (ccr & L2CR_L2I);
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powerpc_sync();
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mtspr(SPR_L2CR, l2cr_config);
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powerpc_sync();
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return (l2cr_config);
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}
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static register_t
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l3_enable(void)
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{
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register_t ccr;
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ccr = mfspr(SPR_L3CR);
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if (ccr & L3CR_L3E)
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return (ccr);
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/* Configure L3 cache. */
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ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN);
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mtspr(SPR_L3CR, ccr);
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ccr |= 0x4000000; /* Magic, but documented. */
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mtspr(SPR_L3CR, ccr);
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ccr |= L3CR_L3CLKEN;
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mtspr(SPR_L3CR, ccr);
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mtspr(SPR_L3CR, ccr | L3CR_L3I);
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while (mfspr(SPR_L3CR) & L3CR_L3I)
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;
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mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN);
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powerpc_sync();
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DELAY(100);
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mtspr(SPR_L3CR, ccr);
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powerpc_sync();
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DELAY(100);
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ccr |= L3CR_L3E;
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mtspr(SPR_L3CR, ccr);
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powerpc_sync();
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return(ccr);
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}
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static register_t
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l1d_enable(void)
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{
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register_t hid;
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hid = mfspr(SPR_HID0);
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if (hid & HID0_DCE)
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return (hid);
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/* Enable L1 D-cache */
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hid |= HID0_DCE;
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powerpc_sync();
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mtspr(SPR_HID0, hid | HID0_DCFI);
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powerpc_sync();
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return (hid);
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}
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static register_t
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l1i_enable(void)
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{
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register_t hid;
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hid = mfspr(SPR_HID0);
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if (hid & HID0_ICE)
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return (hid);
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/* Enable L1 I-cache */
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hid |= HID0_ICE;
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isync();
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mtspr(SPR_HID0, hid | HID0_ICFI);
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isync();
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return (hid);
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}
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uint32_t
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cpudep_ap_bootstrap(void)
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{
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uint32_t hid, msr, reg, sp;
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// reg = mfspr(SPR_MSSCR0);
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// mtspr(SPR_MSSCR0, reg | 0x3);
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__asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
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powerpc_sync();
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__asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid)));
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__asm __volatile("mfspr %0,1023" : "=r"(pcpup->pc_pir));
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msr = PSL_FP | PSL_IR | PSL_DR | PSL_ME | PSL_RI;
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powerpc_sync();
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isync();
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mtmsr(msr);
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isync();
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reg = l3_enable();
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reg = l2_enable();
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reg = l1d_enable();
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reg = l1i_enable();
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hid = mfspr(SPR_HID0);
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hid &= ~(HID0_DOZE | HID0_SLEEP);
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hid |= HID0_NAP | HID0_DPM;
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mtspr(SPR_HID0, hid);
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isync();
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pcpup->pc_curthread = pcpup->pc_idlethread;
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pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
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sp = pcpup->pc_curpcb->pcb_sp;
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return (sp);
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}
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int
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powerpc_smp_start_cpu(struct pcpu *pc)
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{
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phandle_t cpu;
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volatile uint8_t *rstvec;
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int res, reset, timeout;
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cpu = pc->pc_hwref;
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res = OF_getprop(cpu, "soft-reset", &reset, sizeof(reset));
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if (res < 0)
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return (ENXIO);
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ap_pcpu = pc;
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rstvec = (uint8_t *)(0x80000000 + reset);
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*rstvec = 4;
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powerpc_sync();
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DELAY(1);
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*rstvec = 0;
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powerpc_sync();
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timeout = 1000;
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while (!pc->pc_awake && timeout--)
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DELAY(100);
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return ((pc->pc_awake) ? 0 : EBUSY);
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}
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